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| Freescale Semiconductor, Inc. MC68HC05F32 MC68HC05F32/D Freescale Semiconductor, Inc... HC05 MC68HC05F32 MC68HC705F32 TECHNICAL DATA For More Information On This Product, Go to: www.freescale.com TECHNICAL DATA Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. INTRODUCTION MODES OF OPERATION AND PIN DESCRIPTIONS MEMORY AND REGISTERS PARALLEL INPUT/OUTPUT PORTS CORE TIMER 16-BIT PROGRAMABLE TIMER DTMF/MELODY GENERATOR LIQUID CRYSTAL DISPLAY DRIVER MODULE A/D CONVERTER SERIAL PERIPHERAL INTERFACE SERIAL COMMUNICATIONS INTERFACE PULSE WIDTH MODULATOR 32 KHZ CLOCK SYSTEM RESETS AND INTERRUPTS CPU CORE AND INSTRUCTION SET ELECTRICAL SPECIFICATIONS MECHANICAL DATA ORDERING INFORMATION MC68HC705F32 For More Information On This Product, Go to: www.freescale.com 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 A Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 A INTRODUCTION MODES OF OPERATION AND PIN DESCRIPTIONS MEMORY AND REGISTERS PARALLEL INPUT/OUTPUT PORTS CORE TIMER 16-BIT PROGRAMMABLE TIMER DTMF/MELODY GENERATOR LIQUID CRYSTAL DISPLAY DRIVER MODULE A/D CONVERTER SERIAL PERIPHERAL INTERFACE SERIAL COMMUNICATIONS INTERFACE PULSE WIDTH MODULATOR 32 KHZ CLOCK SYSTEM RESETS AND INTERRUPTS CPU CORE AND INSTRUCTION SET ELECTRICAL SPECIFICATIONS MECHANICAL DATA ORDERING INFORMATION MC68HC705F32 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MC68HC05F32 MC68HC705F32 High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit Freescale Semiconductor, Inc... All Trade Marks recognized. This document contains information on new products. Specifications and information herein are subject to change without notice. All products are sold on Motorola's Terms & Conditions of Supply. In ordering a product covered by this document the Customer agrees to be bound by those Terms & Conditions and nothing contained in this document constitutes or forms part of a contract (with the exception of the contents of this Notice). A copy of Motorola's Terms & Conditions of Supply is available on request. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. The Customer should ensure that it has the most up to date version of the document by contacting its local Motorola office. This document supersedes any earlier documentation relating to the products referred to herein. The information contained in this document is current at the date of publication. It may subsequently be updated, revised or withdrawn. (c) MOTOROLA LTD., 1998 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Conventions Where abbreviations are used in the text, an explanation can be found in the glossary, at the back of this manual. Register and bit mnemonics are defined in the paragraphs describing them. An overbar is used to designate an active-low signal, eg: RESET. Unless otherwise stated, shaded cells in a register diagram indicate that the bit is either unused or reserved; `u' is used to indicate an undefined state (on reset). For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. CUSTOMER FEEDBACK QUESTIONNAIRE (MC68HC05F32/D) Motorola wishes to continue to improve the quality of its documentation. We would welcome your feedback on the publication you have just received. Having used the document, please complete this card (or a photocopy of it, if you prefer). 1. How would you rate the quality of the document? Check one box in each category. Excellent Organization Readability Understandability Accuracy Illustrations Comments: Poor Excellent Tables Table of contents Index Page size/binding Overall impression Poor Freescale Semiconductor, Inc... t t t t t t t t t t t t t t t t t t t t t t t Not at all t t t t t t t t t t t t t t t t t t t t 2. What is your intended use for this document? If more than one option applies, please rank them (1, 2, 3). Selection of device for new application System design Training purposes Other t Please specify: 3. How well does this manual enable you to perform the task(s) outlined in question 2? Completely Comments: - Cut along this line to remove - tttt 4. How easy is it to find the information you are looking for? Easy Difficult Comments: tttt 5. Is the level of technical detail in the following sections sufficient to allow you to understand how the device functions? Too little detail SECTION 1 INTRODUCTION SECTION 2 MODES OF OPERATION AND PIN DESCRIPTIONS SECTION 3 MEMORY AND REGISTERS SECTION 4 PARALLEL INPUT/OUTPUT PORTS SECTION 5 CORE TIMER SECTION 6 16-BIT PROGRAMMABLE TIMER SECTION 7 DTMF/MELODY GENERATOR SECTION 8 LIQUID CRYSTAL DISPLAY DRIVER MODULE SECTION 9 A/D CONVERTER SECTION 10 SERIAL PERIPHERAL INTERFACE SECTION 11 SERIAL COMMUNICATIONS INTERFACE SECTION 12 PULSE WIDTH MODULATOR SECTION 13 32 KHZ CLOCK SYSTEM SECTION 14 RESETS AND INTERRUPTS SECTION 15 CPU CORE AND INSTRUCTION SET SECTION 16 ELECTRICAL SPECIFICATIONS SECTION 17 MECHANICAL DATA SECTION 18 ORDERING INFORMATION SECTION 19 APPENDICES Have you found any errors? If so, please comment: Too much detail 6. t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t 7. From your point of view, is anything missing from the document? If so, please say what: For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 8. How could we improve this document? 9. How would you rate Motorola's documentation? Excellent - In general - Against other semiconductor suppliers Poor tttt tttt t t 10. Which semiconductor manufacturer provides the best technical documentation? 11. Which company (in any field) provides the best technical documentation? 12. How many years have you worked with microprocessors? Less than 1 year Freescale Semiconductor, Inc... t 1-3 years t 3-5 years More than 5 years - Second fold back along this line - By air mail Par avion IBRS NUMBER PHQ-B/207/G CCRI NUMERO PHQ-B/207/G NE PAS AFFRANCHIR - Cut along this line to remove - - First fold back along this line - NO STAMP REQUIRED REPONSE PAYEE GRANDE-BRETAGNE Motorola Ltd., Colvilles Road, Kelvin Industrial Estate, EAST KILBRIDE, G75 8BR. GREAT BRITAIN. Semiconductor Products Sector F.A.O. Technical Publications Manager (re: MC68HC05F32/D) - Third fold back along this line - 13. Currently there is some discussion in the semiconductor industry regarding a move towards providing data sheets in electronic form. If you have any opinion on this subject, please comment. 14. We would be grateful if you would supply the following information (at your discretion), or attach your card. Name: Position: Department: Company: Address: Phone No: FAX No: Thank you for helping us improve our documentation, Graham Forbes, Technical Publications Manager, Motorola Ltd., Scotland. For More Information On This Product, Go to: tuck this edge into opposite flap - - Finally, www.freescale.com Freescale Semiconductor, Inc. TABLE OF CONTENTS Paragraph Number TITLE Page Number Freescale Semiconductor, Inc... 1 INTRODUCTION 1.1 1.2 Features................................................................................................................... 1-2 Mask options for the MC68HC05F32 ...................................................................... 1-2 2 MODES OF OPERATION AND PIN DESCRIPTIONS 2.1 2.2 2.2.1 2.2.2 2.2.3 2.3 2.4 2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 Single-chip mode ..................................................................................................... 2-1 Low power modes.................................................................................................... 2-1 STOP mode ....................................................................................................... 2-1 WAIT mode ........................................................................................................ 2-2 Data retention mode .......................................................................................... 2-2 System options register (SOR) ................................................................................ 2-4 Pin descriptions ....................................................................................................... 2-5 VDD and VSS .................................................................................................... 2-5 IRQ .................................................................................................................... 2-5 RESET ............................................................................................................... 2-5 PA7-PA0/keyboard interrupt, PB7-PB0............................................................. 2-5 PC7/SS, PC6/SCK, PC5/MOSI, PC4/MISO, PC3/TDO, PC2/RDI, PC1/TCAP4, PC0/TCAP3 ....................................................................................................... 2-6 2.4.6 PD7-PD0/AN7-AN0 .......................................................................................... 2-6 2.4.7 VRH ................................................................................................................... 2-6 2.4.8 AVDD ................................................................................................................. 2-6 2.4.9 AVSS.................................................................................................................. 2-6 2.4.10 PE7/PWM3, PE6/PWM2, PE5/PWM1, PE4/REFRESH, PE3/TCMP2, PE2/TCAP2, PE1/TCMP1, PE0/TCAP1.................................................................................. 2-6 2.4.11 BP3-BP0 ........................................................................................................... 2-7 2.4.12 VLCD ................................................................................................................. 2-7 2.4.13 Ports F, G, H, I, J/FP39-FP0.............................................................................. 2-7 2.4.14 TNO and TNX .................................................................................................... 2-7 2.4.15 OSC1 and OSC2 ............................................................................................... 2-7 2.4.16 OSC3 and OSC4 ............................................................................................... 2-7 2.4.16.1 Crystal .......................................................................................................... 2-8 TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com TABLE OF CONTENTS MOTOROLA i Freescale Semiconductor, Inc. Paragraph Number Page Number TITLE 2.4.16.2 External clock................................................................................................2-8 2.5 Alternative pin descriptions for the 80-pin QFP package .......................................2-10 2.5.1 PC5, PC4, PC0/TACP3.....................................................................................2-10 2.5.2 PD7-PD0..........................................................................................................2-10 Freescale Semiconductor, Inc... 3 MEMORY AND REGISTERS 3.1 3.2 3.3 3.4 3.5 3.5.1 3.5.2 3.5.3 Registers ..................................................................................................................3-1 RAM .........................................................................................................................3-5 ROM .........................................................................................................................3-5 Bootloader ROM.......................................................................................................3-6 EEPROM ..................................................................................................................3-6 EEPROM programming register .........................................................................3-6 Programming and erasing procedures................................................................3-8 Sample EEPROM programming sequence ........................................................3-8 4 PARALLEL INPUT/OUTPUT PORTS 4.1 Input/output programming ........................................................................................4-1 4.2 Port A........................................................................................................................4-2 4.2.1 Keyboard interrupt ..............................................................................................4-2 4.2.1.1 Key control register (KCR) ............................................................................4-3 4.3 Port B........................................................................................................................4-4 4.4 Port C .......................................................................................................................4-5 4.5 Port D .......................................................................................................................4-5 4.6 Port E........................................................................................................................4-6 4.7 Ports F, G, H, I and J ................................................................................................4-6 4.8 Port registers ............................................................................................................4-7 4.8.1 Port data registers (Ports A, B, C, D, E, F, G, H, I and J) ....................................4-7 4.8.2 Data direction registers (DDRA, DDRB, DDRC, DDRD and DDRE) ..................4-7 4.8.3 Port control registers...........................................................................................4-8 5 CORE TIMER 5.1 5.2 5.2.1 5.2.2 5.3 5.4 5.5 Real time interrupts (RTI) .........................................................................................5-2 Core timer registers ..................................................................................................5-3 Core timer control and status register (CTCSR).................................................5-3 Core timer counter register (CTCR)....................................................................5-4 Computer operating properly (COP) watchdog timer ...............................................5-5 Core timer during WAIT ............................................................................................5-5 Core timer during STOP ...........................................................................................5-5 TPG MOTOROLA ii For More Information On This Product, Go to: www.freescale.com TABLE OF CONTENTS MC68HC05F32 Freescale Semiconductor, Inc. Paragraph Number Page Number TITLE 6 16-BIT PROGRAMMABLE TIMER 6.1 6.1.1 6.2 6.2.1 6.2.2 6.3 6.3.1 6.3.2 6.4 6.4.1 6.4.2 6.5 6.6 6.7 Counter .................................................................................................................... 6-1 Counter register and alternate counter register ................................................. 6-3 Timer control and status .......................................................................................... 6-4 Timer control registers 1 and 2 (TCR1 and TCR2) ............................................ 6-4 Timer status register (TSR)................................................................................ 6-7 Input capture............................................................................................................ 6-9 Input capture register 1 (ICR1) .......................................................................... 6-9 Input capture register 2 (ICR2) ........................................................................ 6-10 Output compare ..................................................................................................... 6-11 Output compare register 1 (OCR1).................................................................. 6-11 Output compare register 2 (OCR2).................................................................. 6-12 Timer during STOP mode...................................................................................... 6-13 Timer during WAIT mode....................................................................................... 6-13 Timer state diagrams ............................................................................................. 6-13 Freescale Semiconductor, Inc... 7 DTMF/MELODY GENERATOR 7.1 7.1.1 7.2 7.3 7.3.1 7.3.2 7.4 7.5 7.6 Introduction .............................................................................................................. 7-1 Features ............................................................................................................. 7-1 Functional description.............................................................................................. 7-2 DMG registers ......................................................................................................... 7-4 Row and column frequency control registers ..................................................... 7-4 Tone control register (TNCR) ............................................................................. 7-4 Operation of the DMG.............................................................................................. 7-7 DMG during WAIT mode.......................................................................................... 7-8 DMG during STOP mode......................................................................................... 7-8 8 LIQUID CRYSTAL DISPLAY DRIVER MODULE 8.1 8.2 8.3 8.4 8.5 8.6 LCD RAM ................................................................................................................ 8-2 LCD operation.......................................................................................................... 8-3 Timing signals and LCD voltage waveforms............................................................ 8-4 LCD control register (LCD) ..................................................................................... 8-9 LCD during WAIT mode......................................................................................... 8-10 LCD during STOP mode........................................................................................ 8-10 MC68HC05F32 For More Information On This Product, Go to: www.freescale.com TABLE OF CONTENTS MOTOROLA iii Freescale Semiconductor, Inc. Paragraph Number Page Number TITLE 9 A/D CONVERTER 9.1 9.2 9.2.1 9.2.2 9.3 9.4 9.5 A/D converter operation............................................................................................9-1 A/D registers.............................................................................................................9-3 A/D status/control register (ADSCR) ..................................................................9-3 A/D result data register (ADDATA) ......................................................................9-5 A/D converter during WAIT mode.............................................................................9-5 A/D converter during STOP mode............................................................................9-5 A/D analog input .......................................................................................................9-5 Freescale Semiconductor, Inc... 10 SERIAL PERIPHERAL INTERFACE 10.1 10.2 10.2.1 10.2.2 10.2.3 10.2.4 10.3 10.4 10.4.1 10.4.2 10.4.3 10.5 10.6 Overview and features............................................................................................10-1 SPI signal descriptions ...........................................................................................10-2 Master in slave out (MISO) ...............................................................................10-2 Master out slave in (MOSI) ...............................................................................10-2 Serial clock (SCK).............................................................................................10-2 Slave select (SS) ..............................................................................................10-4 Functional description ............................................................................................10-4 SPI registers ...........................................................................................................10-6 Control register (SPCR)....................................................................................10-6 Status register (SPSR) .....................................................................................10-8 SPI data I/O register (SPDAT) ..........................................................................10-9 SPI during WAIT mode ...........................................................................................10-9 SPI during STOP mode ..........................................................................................10-9 11 SERIAL COMMUNICATIONS INTERFACE 11.1 SCI two-wire system features.................................................................................11-1 11.2 SCI receiver features ..............................................................................................11-3 11.3 SCI transmitter features..........................................................................................11-3 11.4 External connections ..............................................................................................11-3 11.5 Functional description ............................................................................................11-4 11.6 Data format.............................................................................................................11-5 11.7 Receiver wake-up operation ...................................................................................11-5 11.7.1 Idle line wake-up ...............................................................................................11-6 11.7.2 Address mark wake-up .....................................................................................11-6 11.8 Receive data in (RDI) .............................................................................................11-6 11.9 Start bit detection ...................................................................................................11-7 11.10 Transmit data out (TDO) .........................................................................................11-8 11.11 SCI registers...........................................................................................................11-9 11.11.1 Serial communications data register (SCDAT)..................................................11-9 MOTOROLA iv For More Information On This Product, Go to: www.freescale.com TABLE OF CONTENTS MC68HC05F32 Freescale Semiconductor, Inc. Paragraph Number Page Number TITLE Freescale Semiconductor, Inc... 11.11.2 Serial communications control register 1 (SCCR1) ......................................... 11-9 11.11.3 Serial communications control register 2 (SCCR2) ....................................... 11-11 11.11.4 Serial communications status register (SCSR).............................................. 11-12 11.11.5 Baud rate register (BAUD) ............................................................................. 11-14 11.12 Baud rate selection .............................................................................................. 11-16 11.13 SCI during STOP mode ....................................................................................... 11-16 11.14 SCI during WAIT mode ........................................................................................ 11-16 12 PULSE WIDTH MODULATOR 12.1 12.2 12.3 12.3.1 12.3.2 12.4 12.5 12.6 PWM introduction .................................................................................................. 12-1 Functional description............................................................................................ 12-2 Registers ............................................................................................................... 12-2 PWM control (PWMCR) ................................................................................... 12-3 PWM data registers (PWMD)........................................................................... 12-4 PWM during WAIT mode ....................................................................................... 12-4 PWM during STOP mode ...................................................................................... 12-5 PWM during reset.................................................................................................. 12-5 13 32 KHZ CLOCK SYSTEM 13.1 32 kHz clock system .............................................................................................. 13-1 13.1.1 Custom periodic interrupt control/status register (CPICSR) ............................ 13-1 13.1.1.1 Refresh clock.............................................................................................. 13-2 13.2 Operation during STOP mode ............................................................................... 13-2 13.3 Operation during WAIT mode ................................................................................ 13-2 14 RESETS AND INTERRUPTS 14.1 Resets ................................................................................................................... 14-1 14.1.1 Power-on reset ................................................................................................. 14-1 14.1.2 RESET pin ....................................................................................................... 14-1 14.1.3 Illegal address reset......................................................................................... 14-1 14.1.4 Computer operating properly (COP) reset ....................................................... 14-2 14.1.5 Low voltage reset ............................................................................................. 14-2 14.2 Interrupts ............................................................................................................... 14-3 14.2.1 Interrupt priorities ............................................................................................. 14-4 14.2.2 Non-maskable software interrupt (SWI) ........................................................... 14-4 14.2.3 Maskable hardware interrupts.......................................................................... 14-4 14.2.3.1 Real time and core timer (CTIMER) interrupts ........................................... 14-4 14.2.3.2 Programmable 16-bit timer interrupt........................................................... 14-6 MC68HC05F32 For More Information On This Product, Go to: www.freescale.com TABLE OF CONTENTS MOTOROLA v Freescale Semiconductor, Inc. Paragraph Number 14.2.3.3 14.2.3.4 14.2.3.5 14.2.3.6 14.2.3.7 14.2.4 Page Number TITLE Keyboard interrupt.......................................................................................14-7 Low voltage interrupt...................................................................................14-7 Serial peripheral interface (SPI) interrupt....................................................14-7 Serial communications interface (SCI) interrupt..........................................14-7 Custom periodic interrupt (CPI) ..................................................................14-8 Hardware controlled interrupt sequence...........................................................14-8 Freescale Semiconductor, Inc... 15 CPU CORE AND INSTRUCTION SET 15.1 Registers ................................................................................................................15-1 15.1.1 Accumulator (A) ................................................................................................15-1 15.1.2 Index register (X) ..............................................................................................15-2 15.1.3 Program counter (PC).......................................................................................15-2 15.1.4 Stack pointer (SP).............................................................................................15-2 15.1.5 Condition code register (CCR)..........................................................................15-2 15.2 Instruction set .........................................................................................................15-3 15.2.1 Register/memory Instructions ...........................................................................15-4 15.2.2 Branch instructions ...........................................................................................15-4 15.2.3 Bit manipulation instructions .............................................................................15-4 15.2.4 Read/modify/write instructions..........................................................................15-4 15.2.5 Control instructions ...........................................................................................15-4 15.2.6 Tables................................................................................................................15-5 15.3 Addressing modes..................................................................................................15-5 15.3.1 Inherent.............................................................................................................15-6 15.3.2 Immediate .........................................................................................................15-6 15.3.3 Direct ................................................................................................................15-7 15.3.4 Extended.........................................................................................................15-12 15.3.5 Indexed, no offset ...........................................................................................15-12 15.3.6 Indexed, 8-bit offset ........................................................................................15-12 15.3.7 Indexed, 16-bit offset ......................................................................................15-12 15.3.8 Relative ...........................................................................................................15-13 15.3.9 Bit set/clear .....................................................................................................15-13 15.3.10 Bit test and branch..........................................................................................15-13 16 ELECTRICAL SPECIFICATIONS 16.1 16.2 16.3 16.4 16.5 16.6 16.7 Maximum ratings ....................................................................................................16-1 Thermal characteristics and power considerations ................................................16-2 DC electrical characteristics ...................................................................................16-3 Control timing .........................................................................................................16-5 DC levels for low voltage RESET and LVI ..............................................................16-7 Electrical specifications for DTMF/melody generator .............................................16-7 EEPROM additional information.............................................................................16-8 MOTOROLA vi For More Information On This Product, Go to: www.freescale.com TABLE OF CONTENTS MC68HC05F32 Freescale Semiconductor, Inc. Paragraph Number 16.8 16.9 Page Number TITLE PWM timing ........................................................................................................... 16-8 A/D converter characteristics................................................................................. 16-9 17 MECHANICAL DATA 17.1 17.2 17.3 17.4 100-pin QFP pinout for the MC68HC05F32 .......................................................... 17-1 100-pin QFP mechanical dimensions .................................................................... 17-2 80-pin QFP pinout for the MC68HC05F32 ............................................................ 17-3 80-pin QFP mechanical dimensions ...................................................................... 17-4 Freescale Semiconductor, Inc... 18 ORDERING INFORMATION 18.1 18.2 18.3 EPROMs................................................................................................................ 18-2 Verification media .................................................................................................. 18-2 ROM verification units(RVU).................................................................................. 18-2 A MC68HC705F32 A.1 Features................................................................................................................... A-1 A.2 Pin descriptions ....................................................................................................... A-3 A.2.1 IRQ/VPP ............................................................................................................ A-3 A.3 Memory and registers.............................................................................................. A-3 A.3.1 Registers............................................................................................................ A-3 A.3.2 EPROM ............................................................................................................. A-8 A.3.2.1 EPROM programming register (PROG) ....................................................... A-8 A.3.2.2 EPROM programming operation .................................................................. A-8 A.4 Electrical specifications ........................................................................................... A-9 A.4.1 EPROM characteristics ...................................................................................... A-9 A.4.2 DC levels for low voltage reset and LVI .............................................................. A-9 A.5 Mechanical data .................................................................................................... A-10 A.5.1 100-pin QFP pinout for the MC68HC705F32................................................... A-10 A.5.2 80-pin QFP pinout for the MC68HC705F32..................................................... A-11 GLOSSARY INDEX MC68HC05F32 For More Information On This Product, Go to: www.freescale.com TABLE OF CONTENTS MOTOROLA vii Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA viii For More Information On This Product, Go to: www.freescale.com TABLE OF CONTENTS MC68HC05F32 Freescale Semiconductor, Inc. LIST OF FIGURES Figure Number 1-1 2-1 2-2 3-1 4-1 4-2 5-1 6-1 6-2 6-3 6-4 6-5 7-1 8-1 8-2 8-3 8-4 8-5 8-6 9-1 9-2 10-1 10-2 10-3 11-1 11-2 11-3 11-4 11-5 11-6 11-7 12-1 12-2 TITLE Page Number Freescale Semiconductor, Inc... MC68HC05F32 block diagram ...........................................................................1-3 STOP and WAIT flowcharts ................................................................................2-3 Oscillator connections ........................................................................................2-9 Memory map of the MC68HC05F32 ..................................................................3-2 Structure of port with keyboard interrupt ............................................................4-3 Standard I/O port structure.................................................................................4-4 Core timer block diagram....................................................................................5-1 16-bit programmable timer block diagram ..........................................................6-2 Timer state timing diagram for reset .................................................................6-14 Timer state timing diagram for input capture ....................................................6-14 Timer state timing diagram for output compare ................................................6-15 Timer state timing diagram for timer overflow...................................................6-15 DTMF/melody generator (DMG) block diagram..................................................7-3 LCD system block diagram.................................................................................8-1 Voltage level selection ........................................................................................8-4 LCD waveform with 2 backplanes, 1/2 bias ........................................................8-5 LCD waveform with 2 backplanes, 1/3 bias ........................................................8-6 LCD waveform with 3 backplanes ......................................................................8-7 LCD waveform with 4 backplanes ......................................................................8-8 A/D converter block diagram ..............................................................................9-2 Electrical model of an A/D input pin....................................................................9-6 Data clock timing diagram ................................................................................10-3 Serial peripheral interface block diagram .........................................................10-5 Serial peripheral interface master-slave interconnection .................................10-6 Serial communications interface block diagram ...............................................11-2 SCI and port C..................................................................................................11-3 Data format.......................................................................................................11-5 SCI sampling technique used on all bits...........................................................11-6 SCI examples of start bit sampling technique ..................................................11-7 Artificial start following a framing error .............................................................11-8 SCI start bit following a break...........................................................................11-8 PWM block diagram..........................................................................................12-1 PWM output waveforms (POL = 1, active high)................................................12-2 TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com LIST OF FIGURES MOTOROLA ix Freescale Semiconductor, Inc. Figure Number 12-3 14-1 15-1 15-2 17-1 17-2 17-3 17-4 A-1 A-2 18-1 18-2 Page Number TITLE Freescale Semiconductor, Inc... PWM waveforms (POL = 0, active low) ............................................................ 12-3 Interrupt flowchart ............................................................................................ 14-5 Programming model ......................................................................................... 15-1 Stacking order .................................................................................................. 15-2 100-pin QFP pinout for the MC68HC05F32 ..................................................... 17-1 100-pin QFP mechanical dimensions............................................................... 17-2 80-pin QFP pinout for the MC68HC05F32 ....................................................... 17-3 80-pin QFP mechanical dimensions................................................................. 17-4 MC68HC705F32 block diagram .........................................................................A-2 Memory map of the MC68HC705F32 ................................................................A-4 100-pin QFP pinout for the MC68HC705F32 ...................................................A-10 80-pin QFP pinout for the MC68HC705F32 .....................................................A-11 MOTOROLA x For More Information On This Product, Go to: www.freescale.com LIST OF FIGURES MC68HC05F32 Freescale Semiconductor, Inc. LIST OF TABLES Table Number 1-1 3-1 3-2 4-1 5-1 5-2 7-1 7-2 7-3 7-4 8-1 8-2 8-3 8-4 9-1 9-2 10-1 11-1 11-2 11-3 12-1 13-1 14-1 15-1 15-2 15-3 15-4 15-5 15-6 15-7 15-8 16-1 16-2 TITLE Page Number Freescale Semiconductor, Inc... Data sheet appendices.......................................................................................1-1 Register outline...................................................................................................3-3 Erase modes ......................................................................................................3-7 I/O pin states ......................................................................................................4-5 Example RTI periods ..........................................................................................5-4 Minimum COP reset times..................................................................................5-5 Bit description for DTMF generation...................................................................7-5 Bit description for melody generator...................................................................7-6 Mode of operation for DMG ................................................................................7-6 Effect of tone generation on DMG ......................................................................7-7 LCD RAM organization.......................................................................................8-2 LCD controller operating modes.........................................................................8-3 Frequency selection............................................................................................8-9 Multiplex ratio/backplane selection ...................................................................8-10 A/D clock selection .............................................................................................9-3 A/D channel assignment.....................................................................................9-4 SPI rate selection .............................................................................................10-8 Method of receiver wake-up ...........................................................................11-10 First prescaler stage .......................................................................................11-15 Second prescaler stage..................................................................................11-15 PWM clock rate ................................................................................................12-4 Refresh clock (32.768 kHz crystal)...................................................................13-2 Vector address for interrupts and reset.............................................................14-6 MUL instruction.................................................................................................15-5 Register/memory instructions...........................................................................15-6 Branch instructions ...........................................................................................15-7 Bit manipulation instructions.............................................................................15-7 Read/modify/write instructions .........................................................................15-8 Control instructions...........................................................................................15-8 Instruction set ...................................................................................................15-9 M68HC05 opcode map...................................................................................15-11 Maximum ratings ..............................................................................................16-1 Package thermal characteristics.......................................................................16-2 TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com LIST OF TABLES MOTOROLA xi Freescale Semiconductor, Inc. Table Number 16-3 16-4 16-5 16-6 16-7 16-8 16-9 16-10 16-11 16-12 16-13 18-1 A-1 A-2 A-3 Page Number TITLE Freescale Semiconductor, Inc... DC electrical characteristics (VDD = 5.0 V)...................................................... 16-3 DC electrical characteristics (VDD = 2.7 V)...................................................... 16-4 Control timing (VDD = 5V) ................................................................................ 16-5 Control timing (VDD = 2.7V).............................................................................. 16-6 DC levels for low voltage reset and LVI ............................................................ 16-7 Sine wave tones at TNO................................................................................... 16-7 Square wave tones at TNO .............................................................................. 16-7 TONEX at TNX output ...................................................................................... 16-8 EEPROM additional information....................................................................... 16-8 PWM timing ...................................................................................................... 16-8 A/D converter characteristics ........................................................................... 16-9 MC order numbers ........................................................................................... 18-1 Register outline ..................................................................................................A-5 EPROM characteristics ......................................................................................A-9 DC levels for low voltage reset and LVI ..............................................................A-9 MOTOROLA xii For More Information On This Product, Go to: www.freescale.com LIST OF TABLES MC68HC05F32 Freescale Semiconductor, Inc. 1 1 INTRODUCTION The MC68HC05F32 is a member of the M68HC05 family of HCMOS microcomputers. Its memory configuration comprises 32K bytes of ROM, 920 bytes of RAM and 256 bytes of EEPROM. The on-board features of this device make it particularly suitable for use in highly integrated telephone handsets; the timer and DTMF generator allow for both pulse and tone dialling and, in addition to telephone set-up parameters and features such as last number redial, the EEPROM can typically store up to 12 telephone numbers of 20 digits, even after power has been removed from the circuit. Other features of the device include the keyboard interrupt facility, which allows a direct interface to a telephone keypad, the LCD circuit, which can drive up to 160 segments of an LCD display, and the A/D converter which could be used, for example, as a volume control for a telephone in hands-free mode. A high level of integration has been achieved on the MC68HC05F32 and careful attention has been paid to its low-power and low-voltage performance, a major consideration in many telecommunications applications. The MC68HC05F32 is very well suited to automotive applications; with its 8 analog inputs and many general I/O lines, it is especially useful in applications such as car dashboards. Also, the voltage levels of the LCD driver can be varied using external resistors, and the timer system is capable of driving two stepper motors (e.g. speedometer and odometer), as well as controlling a real time clock. The SCI subsystem is ideal for interfacing to diagnostic equipment, for example, and the on-board EEPROM can be used to store data such as mileage or calibration information. This data sheet is structured such that devices similar to the MC68HC05F32 are described in a set of appendices. Freescale Semiconductor, Inc... Table 1-1 Data sheet appendices Device MC68HC705F32 Appendix Differences from MC68HC05F32 A 32256 bytes EPROM; 496 bytes boot ROM TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com INTRODUCTION MOTOROLA 1-1 1 1.1 * * * * * * * * * * * * Freescale Semiconductor, Inc. Features Fully static design featuring the industry-standard M68HC05 CPU core 32512 bytes of user ROM, plus 16 bytes for vectors 240 bytes of bootloader ROM 920 bytes of RAM plus 20 bytes of LCD RAM 256 bytes of user EEPROM DTMF/melody generator 16-bit programmable timer with four input captures and four output compares (the outputs of two of the output compares are used internally and do not have external connections) 15 stage multipurpose core timer with timer overflow, real time interrupt and COP watchdog LCD driver with 4 backplanes and 40 frontplanes 8-channel, 8-bit analog-to-digital (A/D) converter Power saving STOP and WAIT modes I/O lines - 100 QFP configuration - total of 80 I/O pins configured as: 16 dedicated bidirectional I/O 64 shared with peripherals 80 QFP configuration - total of 69 I/O pins configured as: 16 dedicated bidirectional I/O 53 shared with peripherals Freescale Semiconductor, Inc... - * * * * * * * * * Keyboard interrupt facility on eight of the I/O lines, with high or low voltage level interrupt triggers Hardware interrupt with edge or edge-and-level sensitive interrupt trigger SCI and SPI subsystems On-chip oscillators Three PWM channels Two selectable bus frequencies 32kHz independent clock system Power-on and power-off resets; low voltage detection circuitry (EEPROM) Available in 100-pin QFP and 80-pin QFP The 80-pin version is only a bond option. Pins PE4, PD7-PD0, PC4, PC5 are shared with module functions which cannot work on the 80-pin package. These modules and their corresponding pin functions should not be enabled. Note: TPG MOTOROLA 1-2 For More Information On This Product, Go to: www.freescale.com INTRODUCTION MC68HC05F32 Freescale Semiconductor, Inc. 1 1.2 Mask options for the MC68HC05F32 There are three mask options available on the MC68HC05F32: STOP instruction (enable/disable), COP watchdog timer (enable/disable) and low voltage reset (LVR - enable/disable). These options are programmed during fabrication and must be specified by the customer at the time of ordering. Freescale Semiconductor, Inc... PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 OSC1 OSC2 OSC3 OSC4 Keyboard interrupt 32512 bytes user ROM 240 bytes bootstrap ROM 16 bytes for vectors PWM Port A PWM3 PWM2 PWM1 TCMP2 TCAP2 TCMP1 TCAP1 TCAP3 TCAP4 TDO RDI MISO MOSI SCK SS Timer PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 AVDD VRH VRL/AVSS PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 TNO TNX 256 bytes user EEPROM Port B SCI 920 bytes RAM 20 bytes LCD RAM Oscillator and divider 32 kHz independent clock system, oscillator and divider 2 SPI REFRESH VDD VSS Core timer Periodic interrupt COP watchdog 2 IRQ RESET VLCD BP3 BP2 BP1 BP0 M68HC05 CPU LCD driver FP39 FP38 FP37 FP36 FP35 FP34 FP33 FP32 FP31 FP30 FP29 FP28 FP27 FP26 FP25 FP24 DTMF/ melody generator FP23 FP22 FP21 FP20 FP19 FP18 FP17 FP16 FP15 FP14 FP13 FP12 FP11 FP10 FP9 FP8 Port H Port G Port F Port I PI7 PI6 PI5 PI4 PI3 PI2 PI1 PI0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 Note: When not being used to output the LCD frontplanes, port G and port F pins are input only, while port H, port I and port J pins are output only. Figure 1-1 MC68HC05F32 block diagram PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com INTRODUCTION FP7 FP6 FP5 FP4 FP3 FP2 FP1 FP0 Port J Port D 8-channel A/D converter AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Port C Port E MOTOROLA 1-3 1 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... THIS PAGE LEFT BLANK INTENTIONALLY TPG MOTOROLA 1-4 For More Information On This Product, Go to: www.freescale.com INTRODUCTION MC68HC05F32 Freescale Semiconductor, Inc. 2 2 MODES OF OPERATION AND PIN DESCRIPTIONS The normal operating mode of the MC68HC05F32 is single chip mode. There is also a bootloader mode, primarily for factory test purposes. In addition to these modes, there are three low power modes which may be entered and exited at will from user mode: STOP, WAIT and data retention. Freescale Semiconductor, Inc... 2.1 Single-chip mode This is the normal user operating mode, in which the device functions as a self-contained microcomputer unit, with all on-board peripherals and I/O ports available to the user. All address and data activity occurs within the MCU. 2.2 2.2.1 Low power modes STOP mode The STOP instruction places the MCU in its lowest power consumption mode. In STOP mode, the internal oscillator is turned off, halting all internal processing, including timer (and COP watchdog timer) operation, 16-bit timers, SPI, SCI, PWM and A/D converter. During STOP mode, the core timer interrupt flags (CTOF and RTIF) and interrupt enable bits (TOFE and RTIE) in the CTCSR as well as the 16-bit timer flags in register TSR and interrupt enable bits in register TCR are cleared by internal hardware. The I-bit in the CCR is cleared to enable external interrupts. All other registers, the remaining bits in the CTCSR, and memory contents remain unaltered. All input/output lines remain unchanged. The processor can be brought out of STOP mode only by an interrupt (IRQ, Keyboard, LVI or CPI from the 32 kHz clock system) if enabled or RESET (external reset or low voltage reset - LVR). See Figure 2-1. The STOP instruction can be disables by a mask option. When disabled, the STOP instruction is executed as a NOP. TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com MODES OF OPERATION AND PIN DESCRIPTIONS MOTOROLA 2-1 Freescale Semiconductor, Inc. 2 2.2.2 WAIT mode The WAIT instruction places the MCU in a low power consumption mode, though it consumes more power than in STOP mode. All CPU action is suspended, but the Core timer, the first 16-bit timer (TCAP1, 2 and TCMP1, 2), the DMG and the LCD remain active. If bit 7 (WTLCDO) of the LCD control register, $1E, is reset, the SPI, the SCI, the second 16-bit timer (TCAP3, 4 and TCMP3, 4) and the A/D converter, also remain active in WAIT mode. If, however, WTLCDO is set they are turned off. An interrupt from the core timer, 16-bit timers, SPI, SCI, IRQ, keyboard, LVI, OR CPI from the 32 kHz clock system, if enabled, will cause the MCU to exit the WAIT mode. An external reset, or LVR, causes the MCU to exit the wait mode. During WAIT mode, the I-bit in the CCR is cleared to enable interrupts. All other registers, memory and input/output lines remain in their previous state. See Figure 2-1. Freescale Semiconductor, Inc... 2.2.3 Data retention mode The contents of the RAM and CPU registers are retained at supply voltages as low as 2.0Vdc. This is called the data retention mode, in which data is maintained but the device is not guaranteed to operate. If the voltage drops below VROFF the low voltage reset circuit generates a reset. For lowest power consumption in data retention mode the device should be put into STOP mode before reducing the supply voltage, to ensure that all the clocks are stopped. If the device is not in STOP mode then it is recommended that RESET be held low whilst the power supply is outwith the normal operating range, to ensure that processing is suspended in an orderly manner. Recovery from data retention mode, after the power supply has been restored, is by an external interrupt, or by pulling the RESET line high. TPG MOTOROLA 2-2 MODES OF OPERATION AND PIN DESCRIPTIONS For More Information On This Product, Go to: www.freescale.com MC68HC05F32 Freescale Semiconductor, Inc. 2 STOP WAIT Stop oscillator and all clocks; clear I-mask Oscillator active; stop processing; clear I-mask Freescale Semiconductor, Inc... No RESET ? Yes RESET ? Yes No No Any interrupt ? Yes Any interrupt ? Yes No Turn on oscillator; wait tPORL for stabilization Restart processor clocks Fetch interrupt or RESET vector Fetch interrupt or RESET vector Figure 2-1 STOP and WAIT flowcharts TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com MODES OF OPERATION AND PIN DESCRIPTIONS MOTOROLA 2-3 Freescale Semiconductor, Inc. 2 2.3 System options register (SOR) The MC68HC05F32 MCU contains a System Option Register which is located at address $4D. This register is used to control the LVI and the clock system. Address System options register (SOR) $004D bit 7 LVIF bit 6 LVIE bit 5 LVION bit 4 SC bit 3 bit 2 bit 1 bit 0 State on reset IRQ KEYMUXKEYCLR PUEN 0000 0000 Freescale Semiconductor, Inc... LVIF, LVIE, LVION -- Low voltage interrupt bits The LVIF flag is set by the low voltage detection circuit, if the LVI is enabled and power supply VDD falls below Vlvi. The low voltage interrupt must be enabled by first setting bit LVION Low Voltage Interrupt On and after that setting bit LVIE Low Voltage Interrupt Enable. After power on reset the LVI circuit is disabled. SC -- System clock option After power on reset the internal bus frequency is f=3.58Mhz/2. If the bit SC System Clock is set the system speed is reduced to f=3.58Mhz/4, with the exception of the DTMF generator (Oscillator Frequency 3.58Mhz). IRQ -- Interrupt sensitivity IRQ edge or level sensitivity 1 (set) - IRQ input edge and level sensitive IRQ input edge sensitive 0 (clear) - KEYMUX -- Multiplex bit for access of interrupt flag The KEYMUX bit switches between the port A data register and the interrupt status register IRSTATE, that both have the address $0000. If KEYMUX is cleared normal read and write access to port A is possible. If KEYMUX is set, a read or write operation at address $0000 accesses the 8 interrupt status flags. KEYCLR -- Keyboard interrupt clear The keyboard wake-up interrupt status flag (Bit 7, $1B) is cleared by writing a "1" to bit KEYCLR. A read access to this bit always returns "0". PUEN -- PORTC pull-up enable After power on reset the pull-up resistors in port C are disabled. If bit PUEN is set, the pull-up resistors in port C are enabled. Writing a "0" to PUEN disables the pull-up function. TPG MOTOROLA 2-4 MODES OF OPERATION AND PIN DESCRIPTIONS For More Information On This Product, Go to: www.freescale.com MC68HC05F32 Freescale Semiconductor, Inc. 2.4 2.4.1 Pin descriptions VDD and VSS 2 Power is supplied to the microcomputer via these two pins. VDD is the positive supply pin and VSS is the ground pin. It is in the nature of CMOS designs that very fast signal transitions occur on the MCU pins. These short rise and fall times place very high short-duration current demands on the power supply. To prevent noise problems, special care must be taken to provide good power supply bypassing at the MCU. Bypass capacitors should have good high-frequency characteristics and be as close to the MCU as possible. Bypassing requirements vary, depending on how heavily the MCU pins are loaded. Freescale Semiconductor, Inc... 2.4.2 IRQ This is an input-only pin for external interrupt sources. Interrupt triggering is selected using the IRQ bit in the SOR register, to be one of two options: either edge and level sensitive or edge sensitive only. The IRQ pin contains an internal Schmitt trigger as part of its input to improve noise immunity. 2.4.3 RESET This active low I/O pin is used to reset the MCU. Applying a logic zero to this pin forces the device to a known start-up state. An external RC-circuit can be connected to this pin to generate a power-on reset (POR) if required. In this case, the time constant must be great enough (at least 100ms) to allow the oscillator circuit to stabilise. This input has an internal Schmitt trigger to improve noise immunity. When a low voltage reset condition occurs internally, the RESET pin provides an active-low open drain output signal that may be used to reset external hardware. Other internal reset conditions are not visible at the RESET pin. 2.4.4 PA7-PA0/keyboard interrupt, PB7-PB0 These 16 I/O lines comprise the two 8-bit ports A and B. The state of any pin is software programmable, and on reset, the port pins are configured as inputs, with internal pull-up resistors. The eight I/O lines of port A are shared with the keyboard interrupt function. TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com MODES OF OPERATION AND PIN DESCRIPTIONS MOTOROLA 2-5 Freescale Semiconductor, Inc. 2 2.4.5 PC7/SS, PC6/SCK, PC5/MOSI, PC4/MISO, PC3/TDO, PC2/RDI, PC1/TCAP4, PC0/TCAP3 Freescale Semiconductor, Inc... These eight I/O lines comprise the 8-bit port C, and are shared with other functions to give added flexibility. During reset, these lines are configured as inputs. Port pins PC0 and PC1 are shared with the input timer capture TCAP3 and TCAP4. Pins PC2 and PC3 are connected to the SCI system (RDI, TDO), if the SCI is enabled. The remaining four pins, PC7-PC4, are connected to the SPI system (SS, SCK, MOSI, MISO), if the SPI is enabled. All eight lines have internal programmable pull-ups. If the PUEN bit in the system options register is cleared, the pull-ups are disabled after reset. Setting the PUEN bit enables all the pull-up resistors in port C. 2.4.6 PD7-PD0/AN7-AN0 The eight I/O lines of port D are configured as inputs during power-on or reset. As all port D output are open-drain, an external pull-up resistor is needed when a pin is being used as an output. These port lines, PD7-PD0, are shared with the A/D converter, and are connected to it when the corresponding port D control register bit is set to 1. 2.4.7 VRH The VRH pin is the positive reference voltage for the A/D converter. 2.4.8 AVDD AVDD is the positive supply voltage for the A/D converter. 2.4.9 AVSS AVSS is the negative supply voltage and the negative reference voltage for the A/D converter. 2.4.10 PE7/PWM3, PE6/PWM2, PE5/PWM1, PE4/REFRESH, PE3/TCMP2, PE2/TCAP2, PE1/TCMP1, PE0/TCAP1 The pins PE7-PE0 comprise port E, providing eight I/O lines when the port E control bits are set to 0. As these pins are open-drain, an external pull-up resistor is needed when a pin is being used as an output. These pins also share functions. When the corresponding port E register control bit is set to 1, pins PE3-PE0 are connected to the timer system (TCMP2, TCAP2, TCMP1, TCAP1), pin PE4 becomes REFRESH, and pins PE7-PE5 are connected to the PWM (PWM3-PWM1). TPG MOTOROLA 2-6 MODES OF OPERATION AND PIN DESCRIPTIONS For More Information On This Product, Go to: www.freescale.com MC68HC05F32 Freescale Semiconductor, Inc. 2.4.11 BP3-BP0 The LCD driver subsystem has a maximum of four backplanes and forty frontplanes configured under software control. The pins BP3-BP0 provide the backplane drive signals and the forty output lines FP39-FP0 provide the frontplane drive signals for the LCD unit. The forty frontplane lines are shared with ports F, G, H, I and J. 2 Freescale Semiconductor, Inc... 2.4.12 VLCD The analogue part of the LCD controller can be supplied with an external voltage, VLCD, using the VLCD pin. The value of VLCD may not exceed the positive power supply voltage VDD. When the INTVLCD bit in the LCD control register is set to 1, an internal voltage generator (approx. 3V, if VDD>3V) is activated as the source of the analogue LCD supply voltage. 2.4.13 Ports F, G, H, I, J/FP39-FP0 These five ports are shared with the frontplanes FP39-FP0. The default setting of the register control bits is 0, setting all the pins in ports F and G input only, and all the pins in ports H, I and J output only. The port J outputs are all open-drain. When a register control bit is set to 1, the corresponding pin is connected to the LCD frontplane driver. 2.4.14 TNO and TNX The TNO output provides dual tone DTMF or melody under program control. TNO is an open-drain output, and therefore requires an external pull-up resistor. The TNX output provides pacifier tones under program control. 2.4.15 OSC1 and OSC2 These pins provide control input for an on-chip oscillator circuit. A crystal or external clock signal connected to these pins supplies the oscillator clock. The oscillator frequency of 3.579 MHz provides the time base for the real-time clock and the DTMF/melody generator. 2.4.16 OSC3 and OSC4 These pins provide control input for an independent on-chip oscillator circuit. A 32 kHz crystal connected across these pins, or an external clock signal connected to OSC3 provides the TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com MODES OF OPERATION AND PIN DESCRIPTIONS MOTOROLA 2-7 Freescale Semiconductor, Inc. 2 separate clock. The oscillator frequency (fOSC=32 kHz) provides the time base for the divider, the real time custom periodic interrupt (CPI) and the clock system output (REFRESH). 2.4.16.1 Crystal Freescale Semiconductor, Inc... The circuit shown in Figure 2-2(a) is recommended when using either a crystal or a ceramic resonator. Figure 2-2(d) provides the recommended capacitance and feedback resistance values. The internal oscillator is designed to interface with an AT-cut parallel-resonant quartz crystal resonator in the frequency range specified for fOSC (see Section 16.4). Use of an external CMOS oscillator is recommended when crystals outside the specified ranges are to be used. The crystal and associated components should be mounted as close as possible to the input pins to minimize output distortion and start-up stabilization time. The manufacturer of the particular crystal being considered should be consulted for specific information. 2.4.16.2 External clock An external clock should be applied to the OSC1 input, with the OSC2 pin left unconnected, as shown in Figure 2-2(c). The tOXOV specification (see Section 16.4) does not apply when using an external clock input. The equivalent specification of the external clock source should be used in lieu of tOXOV. TPG MOTOROLA 2-8 MODES OF OPERATION AND PIN DESCRIPTIONS For More Information On This Product, Go to: www.freescale.com MC68HC05F32 Freescale Semiconductor, Inc. 2 L OSC1 C1 RS OSC2 MCU C0 OSC1 RP (b) Crystal equivalent circuit OSC2 Freescale Semiconductor, Inc... C OSC1 C OSC2 MCU OSC1 (a) Crystal resonator oscillator connections OSC2 External clock NC (c) External clock source connections R S (max) C0 C1 C OSC1 C OSC2 RP Q Crystal 2MHz 4MHz 400 75 5 7 8 12 15 - 40 15 - 30 15 - 30 15 - 25 10 10 30 000 40 000 Unit pF nF pF pF M -- (d) Crystal resonator parameters Figure 2-2 Oscillator connections MC68HC05F32 For More Information On This Product, Go to: www.freescale.com MODES OF OPERATION AND PIN DESCRIPTIONS MOTOROLA 2-9 Freescale Semiconductor, Inc. 2 2.5 Alternative pin descriptions for the 80-pin QFP package There is also an 80-pin version of the MC68HC05F32. As it has fewer pins and fewer modules, some of the pin descriptions vary. The reduction of the I/O count means that there is no longer a port H and that port C has only three pins available for use, one of which is shared with the timer (TCAP3). Port D's pins were shared with the A/D converter, but this can no longer be used. Freescale Semiconductor, Inc... 2.5.1 PC5, PC4, PC0/TACP3 The three I/O lines of port C are configured as inputs during reset and each one has an internal pull-up resistor. Pin PC0 is shared with one of the timer's input captures (TCAP3). 2.5.2 PD7-PD0 All eight port D lines are configured as inputs during reset. These pins are open drain outputs which means that each one requires an external pull-up resistor when it is used as an output. MOTOROLA 2-10 MODES OF OPERATION AND PIN DESCRIPTIONS For More Information On This Product, Go to: www.freescale.com MC68HC05F32 Freescale Semiconductor, Inc. 3 MEMORY AND REGISTERS The MC68HC05F32 has a 64K byte memory map consisting of registers (for I/O, control and status), user RAM, user ROM, EEPROM, bootloader ROM and reset and interrupt vectors as shown in Figure 3-1. 3 Freescale Semiconductor, Inc... 3.1 Registers All the I/O, control and status registers of the MC68HC05F32 are contained within the first 80 byte block of the memory map, as detailed in Table 3-1. MC68HC05F32 For More Information On This Product, Go to: www.freescale.com MEMORY AND REGISTERS MOTOROLA 3-1 Freescale Semiconductor, Inc. MC68HC05F32 3 $0000 I/O (80 bytes) $0050 Unused $0054 $0068 RAM (920 bytes) LCD RAM (20 bytes) Freescale Semiconductor, Inc... Stack $0400 EEPROM (256 bytes) $0500 Unused $8000 User ROM (32256 bytes) $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $1A $1B $1C Port A data (PORTA) Port B data (PORTB) Port C data (PORTC) Port D data (PORTD) Port A DDR (DDRA) Port B DDR (DDRB) Port C DDR (DDRC) Port D DDR (DDRD) Ctimer control/status (CTCSR) Ctimer counter (CTCR) Port E data (PORTE) Port E DDR (DDRE) Port E control (PECR) Row freq. control (FCR) Column freq. control (FCC) Tone control (TNCR) Port F data (PORTF) Port F control (PFCR) Port G data (PORTG) Port G control (PGCR) Port H data (PORTH) (1) Port H control (PHCR)(1) Port I data (PORTI) Port I control (PICR) Port J data (PORTJ) Port J control (PJCR) Port D control (PDCR) Key control (KCR) EEPROM prog. (EEPROG) $28 $29 $2A $2B $2C $2D $2E $30 $31 $32 $33 $34 $35 $36 $37 $38 $39 $3A $3B $3C $3D $3E $40 $41 $42 $43 $44 $45 $46 $47 $48 $49 $4A $4B $4C $4D $4E $4F Counter 1 high (CNTH/1) Counter 1 low (CNTL/1) Alt. counter high 1 (ACNTH/1) Alt. counter low 1 (ACNTL/1) Timer 1 control 1 (TCR1/1) Timer 1 control 2 (TCR2/1) Timer 1 status (TSR/1) Capture 3 high (ICR3H) Capture 3 low (ICR3L) Compare 3 high (OCR3H) Compare 3 low (OCR3L) Capture 4 high (ICR4H) Capture 4 low (ICR4L) Compare 4 high (OCR4H) Compare 4 low (OCR4L) Counter 2 high (CNTH/2) Counter 2 low (CNTL/2) Alt. counter high 2 (ACNTH/2) Alt. counter low 2 (ACNTL/2) Timer 2 control 1 (TCR1/2)(1) Timer 2 control 2 (TCR2/2)(1) Timer 2 status (TSR/2)(1) PWM control (PWMCR) PWM data 1 (PWMD1) PWM data 2 (PWMD2) PWM data 3 (PWMD3) SPI control (SPCR) (1) SPI status (SPSR) (1) SPI data I/O (SPDAT) (1) SCI data (SCDAT) (1) SCI control 1 (SCCR1) (1) SCI control 2 (SCCR2) (1) SCI status (SCSR) (1) SCI baud rate (BAUD) (1) CPI control/status (CPICSR) System options (SOR) A/D data (ADDATA) (1) A/D status/control (ADSCR) (1) $FF00 $1E LCD control (LCD) Bootloader ROM (496 bytes) $20 $21 $22 $23 $24 $25 $26 $27 Capture 1 high (ICR1H) Capture 1 low (ICR1L) Compare 1 high (OCR1H) Compare 1 low (OCR1L) Capture 2 high (ICR2H) Capture 2 low (ICR2L) Compare 2 high (OCR2H) Compare 2 low (OCR2L) $FFF0 User vectors (16 bytes) $FFFF (1) Not applicable to 80-pin package. - reserved Figure 3-1 Memory map of the MC68HC05F32 MOTOROLA 3-2 For More Information On This Product, Go to: www.freescale.com MEMORY AND REGISTERS MC68HC05F32 Freescale Semiconductor, Inc. Table 3-1 Register outline Register Name Port A data (PORTA) Key interrupt status (KISR) Port B data (PORTB) Port C data (PORTC) Port D data (PORTD) Port A data direction (DDRA) Port B data direction (DDRB) Port C data direction (DDRC) Port D data direction ((DDRD) Core timer control/status (CTCSR) Core timer counter (CTCR) Port E data (PORTE) Port E data direction (DDRE) Port E control (PECR) DTMF row freq. control (FCR) DTMF column freq. control (FCC) DTMF tone control (TNCR) Port F data (PORTF) Port F control (PFCR) Port G data (PORTG) Port G control (PGCR) Port H data (PORTH) Port H control (PHCR) Port I data (PORTI) Port I control (PICR) Port J data (PORTJ) Port J control (PJCR) Port D control (PDCR) Key control (KCR) EEPROM prog. (EEPROG) Address bit 7 $0000 $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C KF 0 KIE CPEN PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PI7 PI6 PI5 PI4 PI3 PI2 PI1 PI0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0 0 0 MS1 PF7 0 0 MS0 PF6 0 0 0 0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 TOF RTIF TOFE RTIE RTOF RRTIF RT1 RT0 PB7 PC7 PD7 PB6 PC6 PD6 PB5 PC5 PD5 PB4 PC4 PD4 PB3 PC3 PD3 PB2 PC2 PD2 PB1 PC1 PD1 PB0 PC0 PD0 PA7 bit 6 PA6 bit 5 PA5 bit 4 PA4 bit 3 PA3 bit 2 PA2 bit 1 PA1 bit 0 PA0 State on reset undefined 0000 0000 undefined undefined undefined 0000 0000 0000 0000 0000 0000 0000 0000 0000 0011 0000 0000 undefined 0000 0000 0000 0000 3 Freescale Semiconductor, Inc... FCR4 FCR3 FCR2 FCR1 FCR0 undefined FCC4 FCC3 FCC2 FCC1 FCC0 undefined 0 PF2 0 PF1 0 PF0 0000 0000 undefined 0000 0000 undefined 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 TGER TGEC TNOE PF5 PF4 PF3 EDG5 EDG4 EDG3 EDG2 EDG1 EDG0 0000 0000 0 ER1 ER0 LATCH EERC EEPGM 0000 0000 LCD control (LCD) $001E WTLCDO FSEL1 FSEL0 I NTVLCD FDISP MUX4 MUX3 EXTVON 0000 0000 Capture 1 high (ICR1H) Capture 1 low (ICR1L) $0020 $0021 (bit 15) (bit 8) undefined undefined MC68HC05F32 For More Information On This Product, Go to: www.freescale.com MEMORY AND REGISTERS MOTOROLA 3-3 Freescale Semiconductor, Inc. Table 3-1 Register outline Register Name Address bit 7 $0022 $0023 $0024 $0025 $0026 $0027 $0028 $0029 $002A (bit 15) $002B $002C $002D $002E ICI1E 0 IC1F (bit 15) (bit 15) (bit 8) (bit 15) (bit 8) (bit 15) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (bit 8) State on reset undefined undefined undefined undefined undefind undefined (bit 8) 1111 1111 1111 1100 (bit 8) 1111 1111 1111 1100 ICI2E OCI1E TOIE CO1E IEDG1 IEDG2 OLVL1 0000 0uu0 0 IC2F OCI2E OC1F 0 CO2E 0 0 OLVL2 0000 0000 0 uuuu uuu0 3 Compare 1 high (OCR1H) Compare 1 low (OCR1L) Capture 2 high (ICR2H) Capture 2 low (ICR2L) Compare 2 high (OCR2H) Compare 2 low (OCR2L) Counter 1 high (CNTH/1) Counter 1 low (CNTL/1) Alternate counter 1 high (ACNTH/1) Alternate counter 1 low (ACNTL/1) Timer1 control 1 (TCR1/1) Timer1 control 2 (TCR2/1) Timer1 status (TSR/1) Freescale Semiconductor, Inc... TOF TCAP1 TCAP2 OC2F Capture 3 high (ICR3H) Capture 3 low (ICR3L) Compare 3 high (OCR3H) Compare 3 low (OCR3L) Capture 4 high (ICR4H) Capture 4 low (ICR4L) Compare 4 high (OCR4H) Compare 4 low (OCR4L) Counter 1 high (CNTH/1) Counter 1 low (CNTL/1) Alternate counter 2 high (ACNTH/1) Alternate counter 2 low (ACNTL/1) Timer2 control 1 (TCR1/2) Timer2 control 2 (TCR2/2) Timer2 status (TSR/2) $0030 $0031 $0032 $0033 $0034 $0035 $0036 $0037 $0038 $0039 (bit 15) (bit 8) undefined undefined (bit 15) (bit 8) undefined undefined (bit 15) undefined undefined (bit 15) undefined undefined (bit 15) (bit 8) 1111 1111 1111 1100 (bit 8) 1111 1111 1111 1100 $003A (bit 15) $003B $003C $003D $003E ICI3E 0 IC3F ICI4E OCI3E TOIE CO3E IEDG3 IEDG4 0 IC4F OCI4E OC3F 0 CO4E 0 0 0000 0uu0 0000 0000 0 uuuu uuu0 TOF TCAP3 TCAP4 OC4F PWM control (PWMCR) PWM data 1 (PWMD1) PWM data 2 (PWMD2) PWM data 3 (PWMD3) SPI control (SPCR) $0040 $0041 $0042 $0043 $0044 SPIE SPE POL3 POL2 POL1 RA1 RA0 0001 1100 1000 0000 1000 0000 1000 0000 DOD MSTR CPOL CPHA SPR1 SPR0 0000 01uu MOTOROLA 3-4 For More Information On This Product, Go to: www.freescale.com MEMORY AND REGISTERS MC68HC05F32 Freescale Semiconductor, Inc. Table 3-1 Register outline Register Name SPI status (SPSR) SPI data I/O (SPDAT) SCI data (SCDAT) SCI control 1 (SCCR1) SCI control 2 (SCCR2) SCI status (SCSR) SCI baud rate (BAUD) CPI control status (CPICSR) System options (SOR) A/D data (ADDATA) A/D status/control (ADSCR) Address bit 7 $0045 $0046 $0047 $0048 $0049 $004A $004B $004C $004D $004E $004F COCO ADRC ADON 0 CH3 CH2 CH1 CH0 R8 TIE TDRE TCLR 0 LVIF T8 TCIE TC 0 CPIF LVIE 0 RIE RDRF M ILIE IDLE WAKE TE OR 0 RE NF 0 RWU FE 0 SBK 0 bit 6 bit 5 0 bit 4 MODF bit 3 0 bit 2 0 bit 1 0 bit 0 0 State on reset 0000 0000 undefined undefined uu00 0000 0000 0000 1100 0000 SPIF WCOL 3 Freescale Semiconductor, Inc... SCP1 SCP0 RCKB SCR2 SCR1 SCR0 0000 0uuu 0 LVION CPIE SC 0 IRQ 0 RFQ1 RFQ0 0000 0000 KEYMUX KEYCLRPUEN 0000 0000 undefined 0000 0000 u = undefined 3.2 RAM The user RAM consists of 920 bytes of memory, from $0068 to $03FF. This is shared with a 64 byte stack area. The stack begins at $00FF, and may extend down to $00C0. Note: Using the stack area for data storage or temporary work locations requires care to prevent the data from being overwritten due to stacking from an interrupt or subroutine call. 3.3 ROM The user ROM occupies 32512 bytes of memory, from $8000 to $FEFF. In addition, there are 16 bytes of user vectors, from $FFF0 to $FFFF. The Bootloader ROM is located from $FF00 to $FFEF. Note: For compatibility, unused bits (shaded) should always be cleared, when writing to them. MC68HC05F32 For More Information On This Product, Go to: www.freescale.com MEMORY AND REGISTERS MOTOROLA 3-5 Freescale Semiconductor, Inc. 3.4 Bootloader ROM 3 The MC68HC05F32 has 224 bytes of bootloader ROM plus 16 bytes of bootloader vectors, from $FF00 to $FFEF. These are included primarily for factory test purposes. 3.5 EEPROM Freescale Semiconductor, Inc... 256 bytes of user EEPROM reside at addresses $0400 to $04FF. Programming or erasing the EEPROM can be done by the user on a single byte basis; erasing may also be performed on a block or bulk basis. All programming or erasing is accomplished by manipulating the programming register (EEPROG), located at address $001C. Note: The erased state of an EEPROM byte is `$FF'. This means that a write forces zeros to the bits specified, whilst bits defined as ones are unchanged by a write operation. Caution: There is a restriction on the use of indexed addressing for EEPROM read operations. When the base address of an indexed read of an EEPROM location is within the EEPROM address range ($0400 to $04FF), the read may not be successful. e.g. LDA (BASE ADDRESS), X - may not give the correct result when the base address is in the range $0400 to $04FF. However if the base address is outwith the EEPROM address range, the read operation will be successful. This restriction applies to all operations capable of using indexed addressing. 3.5.1 EEPROM programming register Address bit 7 0 bit 6 CPEN bit 5 0 bit 4 ER1 bit 3 bit 2 bit 1 bit 0 State on reset EEPROM programming (EEPROG) $001C ER0 LATCH EERC EEPGM 0000 0000 CPEN -- Charge pump enable 1 (set) - Charge pump enabled. Charge pump disabled. 0 (clear) - When set, CPEN enables the charge pump which produces the internal programming voltage. This bit should be set at the same time as the LATCH bit. The programming voltage will not be available until EEPGM is set. The charge pump should be disabled when not in use. CPEN is readable and writable and is cleared by reset. MOTOROLA 3-6 For More Information On This Product, Go to: www.freescale.com MEMORY AND REGISTERS MC68HC05F32 Freescale Semiconductor, Inc. ER1, ER0 -- Erase select bits ER1 and ER0 are used to select either single byte programming or one of three erase modes: byte, block, or bulk. Table 3-2 shows the mode selected for each bit configuration. These bits are readable and writable and are cleared by reset. 3 Table 3-2 Erase modes ER1 0 0 1 1 ER0 0 1 0 1 Mode Program Byte erase Block erase Bulk erase Freescale Semiconductor, Inc... - - In byte erase mode, only the selected byte is erased. In block erase mode, a 32-byte block of EEPROM is erased. The EEPROM memory space is divided into four 64-byte blocks ($0400 - $043F, $0440 - $047F, $0480 - $04BF and $04C0 - $04FF) and performing a block erase on any address within a block will erase the entire block. In bulk erase mode, the entire 256 bytes of EEPROM are erased. - LATCH -- EEPROM latch bit 1 (set) - EEPROM address and data buses are configured for programming. EEPROM address and data buses are configured for normal operation. 0 (clear) - When set, the LATCH bit configures the EEPROM address and data buses for programming. In addition, writes to the EEPROM array cause the address and data buses to be latched. This bit is readable and writable, but reads from the EEPROM array are inhibited if the LATCH bit is set and a write to the EEPROM space has taken place. When this bit is clear, address and data buses are configured for normal operation. Reset clears this bit. EERC -- EEPROM RC oscillator control 1 (set) - Use internal RC oscillator for EEPROM. Use CPU clock for EEPROM. 0 (clear) - When this bit is set, the EEPROM memory array uses the internal RC oscillator instead of the CPU clock. After setting the EERC bit, the user should wait a time tRCON to allow the RC oscillator to stabilize. This bit is readable and writable and should be set by the user when the internal bus frequency falls below 1.5MHz. Reset clears this bit. MC68HC05F32 For More Information On This Product, Go to: www.freescale.com MEMORY AND REGISTERS MOTOROLA 3-7 Freescale Semiconductor, Inc. EEPGM -- EEPROM programming power enable 1 (set) - Programming power connected to the EEPROM array. Programming power switched off. 3 0 (clear) - Freescale Semiconductor, Inc... EEPGM must be set to enable the EEPGM function. When set, EEPGM turns on the charge pump and enables the programming (or erasing) power to the EEPROM array. When clear, this power is switched off. This will enable pulsing of the programming voltage to be controlled internally. This bit can be read at any time, but can only be written to if LATCH = 1, i.e. if LATCH is not set, then EEPGM cannot be set. Reset clears this bit. 3.5.2 Programming and erasing procedures To program a byte of EEPROM, set LATCH = CPEN = 1, set ER1 = ER0 = 0, write data to the desired address and then set EEPGM for a time tEPGM. There are three possibilities for erasing data from the EEPROM array, depending on how much data is affected. * * * To erase a byte of EEPROM, set LATCH = CPEN = 1, set ER1 = 0 and ER0 = 1, write data to the desired address and then set EEPGM for a time tEBYTE. To erase a block of EEPROM, set LATCH = CPEN = 1, set ER1 = 1 and ER0 = 0, write data to any address in the block and then set EEPGM for a time tEBLOCK. To bulk erase the EEPROM, set LATCH = CPEN = 1, set ER1 = ER0 = 1, write data to any address in the array and then set EEPGM for a time tEBULK. To terminate the programming or erase sequence, clear EEPGM, wait for a time tFPV to allow the programming voltage to fall, and then clear LATCH and CPEN to release the buses. Following each erase or programming sequence, clear all programming control bits. 3.5.3 Sample EEPROM programming sequence The following program is an example of the EEPROM programming sequence, using the timer to implement the required delay and assuming a 1 MHz bus frequency. MOTOROLA 3-8 For More Information On This Product, Go to: www.freescale.com MEMORY AND REGISTERS MC68HC05F32 Freescale Semiconductor, Inc. TCSR EQU TCNT EQU TOF EQU PROG EQU CPEN EQU ER1 EQU ER0 EQU LATCH EQU EERC EQU EEPGM EQU EESTARTEQU SUMPIN EQU ORG START $0008 $0009 7 $001C 6 4 3 2 1 0 $0400 $FF $0680 * EERC, PROG DELAY CPEN, PROG LATCH, PROG ER1, PROG ER0, PROG #SUMPIN EESTART EEPGM, PROG DELAY EEPGM, PROG DELAY LATCH, PROG CPEN, PROG EESTART OUT1 TIMER CONTROL AND STATUS REGISTER TIMER COUNTER REGISTER TOF BIT OF TCSR EEPROM PROGRAM REGISTER CHARGE PUMP ENABLE BIT ERASE SELECT BIT 1 ERASE SELECT BIT 0 LATCH BIT RC/OSC SELECTOR BIT EEPROM PROGRAM BIT START ADDRESS OF EEPROM DUMMY DATA 3 Freescale Semiconductor, Inc... EQU BSET BSR BSET BSET BCLR BCLR LDA STA BSET JSR BCLR JSR BCLR BCLR CMP BNE CLC SELECT RC OSCILLATOR RC OSCILLATOR STABILIZATION TURN ON CHARGE PUMP ENABLE LATCH BIT SELECT PROGRAM (NOT ERASE) SELECT PROGRAM (NOT ERASE) GET DATA ENABLE PROGRAMMING POWER WAIT FOR PROGRAMMING TIME CLEAR EEPGM WAIT FOR PROG VOLTAGE TO FALL CLEAR LATCH DISABLE CHARGE PUMP VERIFY CLEAR CARRY BIT IF NO ERROR OUT OUT1 RTS SEC RTS FLAG AN ERROR *THIS ROUTINE GIVES A 15MS (+/-1MS) DELAY AT 1 MHZ BUS. THE SAME DELAY * ROUTINE IS USED IN THIS EXAMPLE FOR SIMPLICITY, USING THE LONGEST DELAY * TIME. USERS WILL WANT TO WRITE SHORTER DELAY ROUTINES FOR APPLICATIONS *IN WHICH SPEED IS IMPORTANT. DELAY TIMLP EQU LDX BCLR BRCLR DECX BNE RTS * #15 TOF, TCSR TOF, TCSR TIMLP COUNT OF 15 CLEAR TOF WAIT FOR TOF FLAG COUNT DOWN TO 0 MC68HC05F32 For More Information On This Product, Go to: www.freescale.com MEMORY AND REGISTERS MOTOROLA 3-9 Freescale Semiconductor, Inc. 3 Freescale Semiconductor, Inc... THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA 3-10 For More Information On This Product, Go to: www.freescale.com MEMORY AND REGISTERS MC68HC05F32 Freescale Semiconductor, Inc. 4 PARALLEL INPUT/OUTPUT PORTS The MC68HC05F32 has a total of 80 I/O lines, arranged as ten 8-bit ports. The I/O lines are individually programmable as either input or output, under the software control of the data direction registers. Port A can also be configured to respond to keyboard interrupts. To avoid glitches on the output pins, data should be written to the I/O port data register before writing ones to the corresponding data direction register bits to set the pins in output mode. 4 Freescale Semiconductor, Inc... 4.1 Input/output programming The bidirectional port lines may be programmed as inputs or outputs under software control. The direction of each pin is determined by the state of the corresponding bit in the port data direction register (DDR). Each I/O port has an associated DDR. Any I/O port pin is configured as an output if its corresponding DDR bit is set to a logic one. A pin is configured as an input if its corresponding DDR bit is cleared. At power-on or reset, all DDRs are cleared, thus configuring all port pins as inputs. The data direction registers can be written to or read by the MCU. During the programmed output state, a read of the data register actually reads the value of the output data latch and not the I/O pin. The operation of the standard port hardware is shown schematically in Figure 4-2. This is further summarized in Table 4-1, which shows the effect of reading from, or writing to an I/O pin in various circumstances. Note that the read/write signal shown is internal and not available to the user. TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com PARALLEL INPUT/OUTPUT PORTS MOTOROLA 4-1 Freescale Semiconductor, Inc. 4.2 Port A Port A is an 8-bit bidirectional port which is equipped with a keyboard interrupt. All eight lines have internal pull-up resistors, which are required when the port is in input mode. On reset, this port is configured as a standard I/O port comprising a data register and a data direction register. 4 Freescale Semiconductor, Inc... Reset does not affect the state of the data register, but clears the data direction register, thereby returning all ports pins to input mode. Writing a 1 to any DDR bit sets the corresponding port pin to output mode. As every pin configured as an input contributes to the keyboard interrupt, it is possible to disable a single pin by configuring it as an output. 4.2.1 Keyboard interrupt Provided that the interrupt mask bit of the condition code register is cleared, the keyboard interrupt facility is enabled by setting the keyboard interrupt bit (KIE) in the key control register. On detection of a high-to-low transition, the interrupt inputs PA6 and PA7 are triggered. The trigger edges of the interrupt lines, PA0-PA5, can be programmed using the EDG0-EDG5 bits in the key control register. If one of these bits is cleared, after reset the corresponding interrupt is falling-edge sensitive. If, however, one of them is set, after reset the corresponding interrupt is rising-edge sensitive. The internal pull-up resistors of input lines, PA7-PA0, are disabled, if rising-edge sensitivity is selected. When a correct transition is detected, on any of this port's pins, a keyboard interrupt request is generated, and the corresponding interrupt status flag of the interrupt status register, IRSTATE, is set. The interrupt status register is an 8-bit register which has the same address as PORTA, $0000. This register can be read if the KEYMUX bit in the system option register is set. If KIE is set, a keyboard interrupt is generated and the keyboard status flag, KF, is set by generating the logical OR of the eight interrupt state register outputs. The 8 interrupt state register flags can be reset in three ways: 1) Completely, if the chip is reset. 2) Completely, if a 1 is written to KEYCLR, in the system option register. 3) Individually, if a 1 is written to the corresponding bit position of the interrupt state register ($00 with KEYMUX = 1, in the system option register). TPG MOTOROLA 4-2 For More Information On This Product, Go to: www.freescale.com PARALLEL INPUT/OUTPUT PORTS MC68HC05F32 Freescale Semiconductor, Inc. KIE Bit 6, $1B KEYMUX and read PTAIO EDG0 Bit 0, $1B Internal data bit 0 4 D Interrupt state 0 C R 8 Q KF and keyboard interrupt request Freescale Semiconductor, Inc... VDD DDR0 Bit 0, $04 IRST1 - IRST8 Figure 4-1 Structure of port with keyboard interrupt 4.2.1.1 Key control register (KCR) This register contains eight bits, two of which are used to control the keyboard interrupt facility, the others determine the keyboard interrupt edges. Address Key control register (KCR) $001B bit 7 KF bit 6 KIE bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset EDG5 EDG4 EDG3 EDG2 EDG1 EDG0 0000 0000 KF -- Keyboard interrupt status flag 1 (set) - A valid transition has occurred on one of the port pins. No valid transition has occurred on any of the port pins. 0 (clear) - This bit is set when a valid transition is detected on any of the port A pins; a keyboard interrupt request will be generated, if keyboard interrupts are enabled (only if KIE is set). The KF flag is cleared by resetting the IRSTATE register, or by setting KEYCLR = 1 in the system option register. TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com PARALLEL INPUT/OUTPUT PORTS MOTOROLA 4-3 Freescale Semiconductor, Inc. KIE -- keyboard interrupt enable 1 (set) - Keyboard interrupt enabled. Keyboard interrupt disabled. 0 (clear) - An interrupt can only be generated if KIE and KF are both set and the I-bit in the CCR is clear. 4 EDG5-EDG0 -- trigger edge control 1 (set) - Sets the corresponding interrupt line to rising-edge sensitive. Sets the corresponding interrupt line falling-edge sensitive. Freescale Semiconductor, Inc... 0 (clear) - The trigger edges of the interrupt lines PA5-PA0 are programmable with the EDG5-EDG0 bits in the key control register. 4.3 Port B This port is a standard M68HC05 bidirectional I/O port, comprising a data register and a data direction register. Reset does not affect the state of the data register, but clears the data direction register, thereby returning all port pins to input mode. Writing a `1' to any DDR bit sets the corresponding port pin to output mode. The port B lines have internal pull-up resistors. M68HC05 inter nal connections Data direction register bit DDRn Latched data register bit DATA Output buffer I/O pin Output DDRn 1 1 0 0 DATA 0 1 0 1 I/O 0 1 tristate tristate O/P data buffer Input buffer Input Figure 4-2 Standard I/O port structure TPG MOTOROLA 4-4 For More Information On This Product, Go to: www.freescale.com PARALLEL INPUT/OUTPUT PORTS MC68HC05F32 Freescale Semiconductor, Inc. Table 4-1 I/O pin states R/W 0 0 1 1 DDRn 0 1 0 1 Action of MCU write to/read of data bit The I/O pin is in input mode. Data is written into the output data latch. Data is written into the output data latch, and output to the I/O pin. The state of the I/O pin is read. The I/O pin is in output mode. The output data latch is read. 4 Freescale Semiconductor, Inc... 4.4 Port C Port C is an 8-bit bidirectional port, which is shared with the SPI subsystem, the SCI subsystem and the timer system. If the SPI system is enabled, pins PC4-PC7 are connected to the functions MISO, MOSI, SCK and SS, respectively. It the SCI system is enabled, pins PC2 and PC3 are connected to RDI and TDO. PC0 and PC1 are connected to TCAP3 and TCAP4 in the timer system. (These lines must be set to input, by resetting the DDR, to enable the correct TCAP function). Reset does not affect the data register, but it clears the data direction register, returning the ports to inputs. Writing a 1 to a DDR bit, sets the corresponding port bit to output mode. All eight lines have internal pull-ups, which can be programmed using the PUEN bit in the system option register (SOR). The internal pull-ups are disabled after reset and when PUEN = 0, but are enabled by writing a 1 to PUEN. 4.5 Port D Port D is an 8-bit bidirectional port, which is shared with the A/D converter. A pin becomes connected to the A/D converter, when its corresponding bit in the control register is set to 1. Reset does not affect the data register, but it clears the data direction register and the control register. The default setting of the register control bits is 0, making the pins general purpose I/O lines. The direction of the pins is then determined by their corresponding bits in DDR (0 - input, 1 - output). Write access to DDR or the I/O register is blocked to reduce digital noise. Read access to DDR or the I/O register returns 0. Port D has open-drain outputs, it therefore requires external pull-up resistors for each pin when they are used as outputs. Note: The maximum leakage current for I/O ports is 10A. Thus, a high resistance from an analog source can limit the accuracy of the A/D converter. The analog source should therefore be less than 1 k. TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com PARALLEL INPUT/OUTPUT PORTS MOTOROLA 4-5 Freescale Semiconductor, Inc. 4.6 Port E 4 Freescale Semiconductor, Inc... Port E is an 8-bit bidirectional port which is shared with the timer system, the independent 32 kHz clock system and the PWM. When the corresponding bit in the port E control register is set to 1, the pins PE1 and PE3 are connected to TCMP1 and TCMP2 of the timer system, PE4 is connected to the independent clock system, it becomes REFRESH, and PE5 - PE7 become PWM1 - PWM3 of the PWM system. Pins PE0 and PE2 are always connected to the timer system (TCAP1 and TCAP2). These two lines must be set to input by resetting the DDR to enable correct TCAP function. Reset does not affect the data register, but it clears the data direction register and the control register. The default setting of the register control bits is 0, making the pins general purpose I/O lines. The direction of the pins is then determined by their corresponding bits in DDR (0 - input, 1 - output). Port E has open-drain outputs, it therefore requires external pull-up resistors for each pin when they are used as outputs. Note: As the voltage at port D or port E is driven above VDD, the protection device will begin to conduct and tend to clamp the input voltage to protect the input buffer. The voltage at which this condition will occur varies significantly, from lot to lot, and over the temperature range. At room temperature, the pin typically does not draw any current until approximately 18V. 4.7 Ports F, G, H, I and J These five ports are shared with the frontplanes FP39 - FP0. The default setting of the port control bits, during reset, is 0, setting the pins in port F and port G to input only, and the pins in ports H, I and J, to output only. At power on or reset, the output only port data registers are cleared, so that these pins are driving logical 0. When the corresponding port control register bit is set to a 1, the pin is connected to the LCD frontplane driver. All port J outputs are open-drain. TPG MOTOROLA 4-6 For More Information On This Product, Go to: www.freescale.com PARALLEL INPUT/OUTPUT PORTS MC68HC05F32 Freescale Semiconductor, Inc. 4.8 Port registers The following sections explain in detail the individual bits in the data and control registers associated with the ports. 4.8.1 Port data registers (Ports A, B, C, D, E, F, G, H, I and J) Address bit 7 PA7 PB7 PC7 PD7 PE7 PF7 PG7 PH7 PI7 PJ7 bit 6 PA6 PB6 PC6 PD6 PE6 PF6 PG6 PH6 PI6 PJ6 bit 5 PA5 PB5 PC5 PD5 PE5 PF5 PG5 PH5 PI5 PJ5 bit 4 PA4 PB4 PC4 PD4 PE4 PF4 PG4 PH4 PI4 PJ4 bit 3 PA3 PB3 PC3 PD3 PE3 PF3 PG3 PH3 PI3 PJ3 bit 2 PA2 PB2 PC2 PD2 PE2 PF2 PG2 PH2 PI2 PJ2 bit 1 PA1 PB1 PC1 PD1 PE1 PF1 PG1 PH1 PI1 PJ1 bit 0 PA0 PB0 PC0 PD0 PE0 PF0 PG0 PH0 PI0 PJ0 State on reset 4 Freescale Semiconductor, Inc... Port A data (PORTA) Port B data (PORTB) Port C data (PORTC) Port D data (PORTD) Port E data (PORTE) Port F data (PORTF) Port G data (PORTG) Port H data (PORTH) Port I data (PORTI) Port J data (PORTJ) $0000 $0001 $0002 $0003 $000A $0010 $0012 $0014 $0016 $0018 undefined undefined undefined undefined undefined undefined undefined 0000 0000 0000 0000 0000 0000 Each bit of port A - port E can be configured as input or output via the corresponding data direction bit in the port data direction register (DDRx). Reset does not affect the state of the port A - port G data registers. However, port H, port I and port J data registers are reset to 0. 4.8.2 Data direction registers (DDRA, DDRB, DDRC, DDRD and DDRE) Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Port A data direction (DDRA) Port B data direction (DDRB) Port C data direction (DDRC) Port D data direction (DDRD) Port E data direction (DDRE) $0004 $0005 $0006 $0007 $000B Writing a `1' to any bit configures the corresponding port pin as an output; conversely, writing any bit to `0' configures the corresponding port pin as an input. Reset clears these registers, thus configuring all port pins as inputs. TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com PARALLEL INPUT/OUTPUT PORTS MOTOROLA 4-7 Freescale Semiconductor, Inc. 4.8.3 Port control registers State on reset$ 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 4 Freescale Semiconductor, Inc... Port D control (PDCR) Port E control (PECR) Port F control (PFCR) Port G control (PGCR) Port H control (PHCR) Port I control (PICR) Port J control (PJCR) $001A $000C $0011 $0013 $0015 $0017 $0019 Writing a 1 to any bit configures the corresponding port pin as a special function port (timer, A/D, LCD, PWM, refresh clock). However, clearing any bit to 0, configures the corresponding port pin in port D and port E as general purpose I/O, port F and port G as input, and port H, port I and port J as output. TPG MOTOROLA 4-8 For More Information On This Product, Go to: www.freescale.com PARALLEL INPUT/OUTPUT PORTS MC68HC05F32 Freescale Semiconductor, Inc. 5 CORE TIMER The MC68HC05F32 has a 15-stage ripple counter called the core timer (CTIMER). Features of this timer are: timer overflow, power-on reset (POR), real time interrupt (RTI) with four selectable interrupt rates and a computer operating properly (COP) watchdog timer. Freescale Semiconductor, Inc... 5 Internal bus 8 Internal processor clock $09 CTCR (Core timer counter) 8 fOP / 210 7-bit counter Overflow detect circuit fOP fOP / 22 (/ 4) fOP / 217 RTI select circuit $08 CTCSR (Core timer control and status) fOP / 214 COP clear 8 TOF RTIF TOFE RTIE RTOF RRTIF RT1 RT0 COP watchdog timer (/ 8) Interrupt circuit To reset logic To interrupt logic Figure 5-1 Core timer block diagram TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com CORE TIMER MOTOROLA 5-1 Freescale Semiconductor, Inc. As shown in Figure 5-1, the timer is driven by the internal bus clock divided by four with a fixed prescaler. This signal drives an 8-bit ripple counter. The value of this 8-bit ripple counter can be read by the CPU at any time, by accessing the CTIMER counter register (CTCR) at address $09. A timer overflow function is implemented on the last stage of this counter, giving a possible interrupt at the rate of fOP/1024. (The POR signal (tPORL) is also derived from this register, at fOP/4064.) The counter register circuit is followed by four more stages, with the resulting clock (fOP/16384) driving the real time interrupt circuit. The RTI circuit consists of three divider stages with a 1-of-4 selector. The output of the RTI circuit is further divided by 8 to drive the COP watchdog timer circuit. The RTI rate selector bits, and the RTI and CTIMER overflow enable bits and flags, are located in the CTIMER control and status register (CTCSR) at location $08. CTOF (core timer overflow flag) is a clearable, read-only status bit and is set when the 8-bit ripple counter rolls over from $FF to $00. A CPU interrupt request will be generated if CTOFE is set. Clearing the CTOF is done by writing a `0' to it. Writing a `1' to CTOF has no effect on the bit's value. Reset clears CTOF. When CTOFE (core timer overflow enable) is set, a CPU interrupt request is generated when the CTOF bit is set. Reset clears CTOFE. The core timer counter register (CTCR) is a read-only register that contains the current value of the 8-bit ripple counter at the beginning of the timer chain. This counter is clocked at fOP/4 and can be used for various functions including a software input capture. Extended time periods can be attained using the CTIMER overflow function to increment a temporary RAM storage location thereby simulating a 16-bit (or more) counter. The power-on cycle clears the entire counter chain and begins clocking the counter. After tPORL cycles, the power-on reset circuit is released, which again clears the counter chain and allows the device to come out of reset. At this point, if RESET is not asserted, the timer will start counting up from zero and normal device operation will begin. When RESET is asserted at any time during operation (other than POR), the counter chain will be cleared. Freescale Semiconductor, Inc... 5 5.1 Real time interrupts (RTI) The real time interrupt circuit consists of a three stage divider and a 1-of-4 selector. The clock frequency that drives the RTI circuit is fOP/214 (or fOP/16384), with three additional divider stages, giving a maximum interrupt period of 4 seconds at a bus frequency (fOP) of 32kHz. Register details are given in Section 5.2. TPG MOTOROLA 5-2 For More Information On This Product, Go to: www.freescale.com CORE TIMER MC68HC05F32 Freescale Semiconductor, Inc. 5.2 5.2.1 Core timer registers Core timer control and status register (CTCSR) Address Core timer control/status (CTCSR) $0008 bit 7 CTOF bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 RT1 bit 0 RT0 State on reset RTIF CTOFE RTIE RTOF RRTIF 0000 0011 Freescale Semiconductor, Inc... CTOF -- Core timer overflow 1 (set) - Core timer overflow has occurred. No core timer overflow interrupt has been generated. 5 0 (clear) - CTOF is a read-only status bit and is set when the core timer counter register rolls over from $FF to $00; an interrupt request will be generated if CTOFE is set. When set, CTOF may be cleared by writing a `1' to RTOF. RTIF -- Real time interrupt flag 1 (set) - A real time interrupt has occurred. No real time interrupt has been generated. 0 (clear) - RTIF is a read-only status bit and is set when the output of the chosen stage becomes active; an interrupt request will be generated if RTIE is set. When set, the bit may be cleared by writing a `1' to RRTIF. Reset also clears this bit. CTOFE -- Core timer overflow enable 1 (set) - Core timer overflow interrupt is enabled. Core timer overflow interrupt is disabled. 0 (clear) - Setting this bit enables the core timer overflow Interrupt. A CPU interrupt request will then be generated whenever the CTOF bit becomes set and the I-bit in the CCR is clear. Clearing this bit disables the core timer overflow interrupt capability. RTIE -- Real time interrupt enable 1 (set) - Real time interrupt is enabled. Real time interrupt is disabled. 0 (clear) - Setting this bit enables the real time interrupt. A CPU interrupt request will then be generated whenever the RTIF bit becomes set and the I-bit in the CCR is clear. Clearing this bit disables the real time interrupt capability. TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com CORE TIMER MOTOROLA 5-3 Freescale Semiconductor, Inc. RT1, RT0 -- Real time interrupt rate select These two bits select one of four taps from the real time interrupt circuitry. Reset sets both RT0 and RT1 to one, selecting the lowest periodic rate and therefore the maximum time in which to alter them if necessary. The COP reset times are also determined by these two bits. Care should be taken when altering RT0 and RT1 if a timeout is imminent, or the timeout period is uncertain. If the selected tap is modified during a cycle in which the counter is switching, an RTIF could be missed or an additional one could be generated. To avoid problems, the COP should be cleared before changing the RTI taps. See Table 5-1 for some example RTI periods. Freescale Semiconductor, Inc... 5 Table 5-1 Example RTI periods RTI Rates at fOP Frequency Specified Division 16.384 kHz 447 kHz 895 kHz 1.789 MHz ratio 14 2 1s 36.7 ms 18.35 ms 9.17 ms 2 15 2s 73.4 ms 36.7 ms 18.35 ms 2 16 4s 146.8 ms 73.4 ms 36.7 ms 2 17 8s 293.6 ms 146.8 ms 73.4 ms RT1 RT0 0 0 1 1 0 1 0 1 5.2.2 Core timer counter register (CTCR) Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset 0000 0000 Core timer counter (CTCR) $0009 The core timer counter register is a read-only register, which contains the current value of the 8-bit ripple counter at the beginning of the timer chain. Reset clears this register. TPG MOTOROLA 5-4 For More Information On This Product, Go to: www.freescale.com CORE TIMER MC68HC05F32 Freescale Semiconductor, Inc. 5.3 Computer operating properly (COP) watchdog timer The COP watchdog timer function is implemented by taking the output of the RTI circuit and further dividing it by eight, as shown in Figure 5-1. Note that the minimum COP timeout period is seven times the RTI period. This is because the COP will be cleared asynchronously with respect to the value in the core timer counter register/RTI divider, hence the actual COP timeout period will vary between 7x and 8x the RTI period. The minimum COP reset rates are shown in Table 5-2. The COP function is a mask option, enabled or disabled during device manufacture. If the COP circuit times out, an internal reset is generated and the normal reset vector is fetched. A COP timeout is prevented by writing a `0' to bit 0 of address $FFF0. When the COP is cleared, only the final divide-by-eight stage is cleared (see Figure 5-1). Freescale Semiconductor, Inc... 5 Table 5-2 Minimum COP reset times Minimum COP reset at f OP frequency specified 16.384 kHz 447 kHz 895 kHz 1.789 MHz f OP 7s 256.9 ms 128.45 ms 64.19 ms 7 x RTI rate 14 s 513.8 ms 256.9 ms 128.45 ms 7 x RTI rate 28 s 1.03 s 513.8 s 256.9 ms 7 x RTI rate 56 s 2.06 s 1.03 s 513.8 ms 7 x RTI rate RT1 0 0 1 1 RT0 0 1 0 1 5.4 Core timer during WAIT The CPU clock halts during the WAIT mode, but the timer remains active. If the CTIMER interrupts are enabled, then a CTIMER interrupt will cause the processor to exit the WAIT mode. 5.5 Core timer during STOP The timer is cleared when going into STOP mode. When STOP is exited by an external interrupt or an external reset, the internal oscillator will restart, followed by an internal processor stabilization delay (tPORL). The timer is then cleared and operation resumes. TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com CORE TIMER MOTOROLA 5-5 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... 5 THIS PAGE LEFT BLANK INTENTIONALLY TPG MOTOROLA 5-6 For More Information On This Product, Go to: www.freescale.com CORE TIMER MC68HC05F32 Freescale Semiconductor, Inc. 6 16-BIT PROGRAMMABLE TIMER The MC68HC05F32 has two programmable 16-bit timers (TIMER1 and TIMER2), each with two channels. The output compare function in TIMER2 has no external output, and is therefore used for generating precision time intervals and interrupts only. The external connections are the only differences between the two timers. The internal operation is identical (each timer has its own set of registers), therefore only a complete description of TIMER1 is given. The timer consists of a 16-bit read-only free-running counter, with a fixed divide-by-four prescaler, plus the input capture/output compare circuitry. The timer can be used for many purposes including measuring pulse length of two input signals and generating two output signals. Pulse lengths for both input and output signals can vary from several microseconds to many seconds. The timer is also capable of generating periodic interrupts or indicating passage of an arbitrary multiple of four CPU cycles. A block diagram is shown in Figure 6-1, and timing diagrams are shown in Figure 6-2, Figure 6-3, Figure 6-4 and Figure 6-5. The timer has a 16-bit architecture, hence each specific functional segment is represented by two 8-bit registers. These registers contain the high and low byte of that functional segment. Accessing the low byte of a specific timer function allows full control of that function; however, an access of the high byte inhibits that specific timer function until the low byte is also accessed. The 16-bit programmable timer is monitored and controlled by a group of fifteen registers, full details of which are contained in this section. Freescale Semiconductor, Inc... 6 Note: A problem may arise if an interrupt occurs in the time between the high and low bytes being accessed. To prevent this, the I-bit in the condition code register (CCR) should be set while manipulating both the high and low byte register of a specific timer function, ensuring that an interrupt does not occur. 6.1 Counter The key element in the programmable timer is a 16-bit, free-running counter or counter register, preceded by a prescaler that divides the internal processor clock by four. The prescaler gives the timer a resolution of 2s if the internal bus clock is 2 MHz. The counter is incremented during the low portion of the internal bus clock. Software can read the counter at any time without affecting its value. TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com 16-BIT PROGRAMMABLE TIMER MOTOROLA 6-1 Freescale Semiconductor, Inc. Internal bus 8 Internal processor clock High byte Output compare register 1 Low byte $0022 $0023 High byte Output compare register 2 Low byte $0026 $0027 /4 High byte 8-bit buffer Low byte High byte Low byte High byte Low byte Freescale Semiconductor, Inc... 6 16-bit $0028 free-running $0029 counter Counter alternate register $002A $002B Input capture $0020 register 1 $0021 Input capture $0024 register 2 $0025 COP watchdog counter input Internal timer bus Output compare circuit 1 Output compare circuit 2 Overflow detect circuit Edge detect circuit 1 Edge detect circuit 2 TCAP2 pin TCAP1 pin D CLK C Q TCMP2 pin D CLK C OC2IE CO2E OLVL2 TCR2 $002D Q TCMP1 pin IC1F IC2F OC1F TOF OC2F TSR $002E IC1IE IC2IE OC1IE TOIE CO1E IEDG1 IEDG2 OLVL1 TCR1 $002C Interrupt circuit Input capture interrupt vector $7FF4, 5 Output compare interrupt vector $7FF4, 5 Input capture Output compare interrupt vector interrupt vector $7FF4, 5 $7FF4, 5 Overflow interrupt vector $7FF4, 5 RESET Figure 6-1 16-bit programmable timer block diagram TPG MOTOROLA 6-2 For More Information On This Product, Go to: www.freescale.com 16-BIT PROGRAMMABLE TIMER MC68HC05F32 Freescale Semiconductor, Inc. 6.1.1 Counter register and alternate counter register Address Timer counter high (CNTH) Timer counter low (CNTL) $0028 $0029 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset 1111 1111 1111 1100 State on reset 1111 1111 1111 1100 Freescale Semiconductor, Inc... Address Alternate counter high (ACNTH) Alternate counter low (ACNTL) $002A $002B bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 The double-byte, free-running counter can be read from either of two locations, $0028 - $0029 (counter register) or $002A - $002B (counter alternate register). A read from only the less significant byte (LSB) of the free-running counter ($0029 or $002B) receives the count value at the time of the read. If a read of the free-running counter or alternate counter register first addresses the more significant byte (MSB) ($0028 or $002A), the LSB is transferred to a buffer. This buffer value remains fixed after the first MSB read, even if the user reads the MSB several times. This buffer is accessed when reading the free-running counter or alternate counter register LSB and thus completes a read sequence of the total counter value. In reading either the free-running counter or alternate counter register, if the MSB is read, the LSB must also be read to complete the sequence. If the timer overflow flag (TOF) is set when the counter register LSB is read then a read of the timer status register (TSR) will clear the flag. The counter alternate register differs from the counter register only in that a read of the LSB does not clear TOF. Therefore, where it is critical to avoid the possibility of missing timer overflow interrupts due to clearing of TOF, the alternate counter register should be used. The free-running counter is set to $FFFC during power-on and external reset and is always a read-only register. During a power-on reset, the counter begins running after the oscillator start-up delay. Because the free-running counter is 16 bits preceded by a fixed divide-by-4 prescaler, the value in the free-running counter repeats every 262,144 internal bus clock cycles. TOF is set when the counter overflows (from $FFFF to $0000); this will cause an interrupt if TOIE is set. The divide-by-4 prescaler is also reset and the counter resumes normal counting operation. All of the flags and enable bits remain unaltered by this operation. If access has previously been made to the high byte of the free-running counter ($0028 or $002A), then the reset counter operation terminates the access sequence. Caution: This operation may affect the function of the watchdog system (see Section 5.3). 6 TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com 16-BIT PROGRAMMABLE TIMER MOTOROLA 6-3 Freescale Semiconductor, Inc. 6.2 Timer control and status The various functions of the timer are monitored and controlled using the timer control and status registers described below. 6.2.1 Timer control registers 1 and 2 (TCR1 and TCR2) Freescale Semiconductor, Inc... 6 The two timer control registers TCR1 and TCR2 ($002C and $002D) are used to enable the input captures (IC1IE and IC2IE), output compares (OC1IE and OC2E), and timer overflow (TOIE) functions as well as enabling the compare outputs (CO1E and CO2E), selecting input edge sensitivity (IEDG1 and IEDG2) and levels of output polarity (OLVL1 and OLVL2). Address Timer control 1 (TCR1) $002C bit 7 IC1IE bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset IC2IE OC1IE TOIE CO1E IEDG1 IEDG2 OLVL1 0000 0uu0 State on reset Address Timer control 2 (TCR2) $002D bit 7 0 bit 6 0 bit 5 OC2IE bit 4 0 bit 3 CO2E bit 2 0 bit 1 0 bit 0 OLVL2 0000 0000 TPG MOTOROLA 6-4 For More Information On This Product, Go to: www.freescale.com 16-BIT PROGRAMMABLE TIMER MC68HC05F32 Freescale Semiconductor, Inc. IC1IE -- Input capture 1 interrupt enable If this bit is set, a timer interrupt is enabled whenever the IC1F status flag (in the timer status register) is set. 1 (set) - Interrupt enabled. Interrupt disabled. 0 (clear) - IC2IE -- Input capture 2 interrupt enable If this bit is set, a timer interrupt is enabled whenever the IC2F status flag (in the timer status register) is set. 1 (set) - Interrupt enabled. Interrupt disabled. Freescale Semiconductor, Inc... 0 (clear) - 6 OC1IE -- Output compare 1 interrupt enable If this bit is set, a timer interrupt is enabled whenever the OC1F status flag (in the timer status register) is set. 1 (set) - Interrupt enabled. Interrupt disabled. 0 (clear) - TOIE -- Timer overflow interrupt enable If this bit is set, a timer interrupt is enabled whenever the TOF status flag (in the timer status register) is set. 1 (set) - Interrupt enabled. Interrupt disabled. 0 (clear) - CO1E -- Timer compare 1 output enable If this bit is set, the output from timer output compare 1 is enabled. 1 (set) - Output compare 1 enabled. Output compare 1 disabled. 0 (clear) - IEDG1 -- Input edge 1 When IEDG1 is set, a positive-going edge on the TCAP1 pin will trigger a transfer of the free-running counter value to the input capture register 1. When clear, a negative-going edge triggers the transfer. 1 (set) - TCAP1 is positive-going edge sensitive. TCAP1 is negative-going edge sensitive. 0 (clear) - TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com 16-BIT PROGRAMMABLE TIMER MOTOROLA 6-5 Freescale Semiconductor, Inc. IEDG2 -- Input edge 2 When IEDG2 is set, a positive-going edge on the TCAP2 pin will trigger a transfer of the free-running counter value to the input capture register 2. When clear, a negative-going edge triggers the transfer. 1 (set) - TCAP2 is positive-going edge sensitive. TCAP2 is negative-going edge sensitive. 0 (clear) - Freescale Semiconductor, Inc... OLVL1 -- Output level 1 When OLV1 is set a high output level will be clocked into the output level register by the next successful output compare, and will appear on the TCMP1 pin. When clear, it will be a low level which will appear on the TCMP1 pin. 1 (set) - A high output level will appear on the TCMP1 pin. A low output level will appear on the TCMP1 pin. 6 0 (clear) - OC2IE -- Output compare 2 interrupt enable If this bit is set, a timer interrupt is enabled whenever the OC2F status flag (in the timer status register) is set. 1 (set) - Interrupt enabled. Interrupt disabled. 0 (clear) - CO2E -- Timer compare 2 output enable If this bit is set, the output from timer output compare 2 is enabled. 1 (set) - Output compare 2 enabled. Output compare 2 disabled. 0 (clear) - OLVL2 -- Output level 2 When OLV2 is set a high output level will be clocked into the output level register by the next successful output compare, and will appear on the TCMP2 pin. When clear, it will be a low level which will appear on the TCMP2 pin. 1 (set) - A high output level will appear on the TCMP2 pin. A low output level will appear on the TCMP2 pin. 0 (clear) - TPG MOTOROLA 6-6 For More Information On This Product, Go to: www.freescale.com 16-BIT PROGRAMMABLE TIMER MC68HC05F32 Freescale Semiconductor, Inc. 6.2.2 Timer status register (TSR) The timer status register ($002E) contains the status bits corresponding to the timer interrupt conditions - IC1F, IC2F, OC1F, TOF, TCAP1, TCAP2 and OC2F. Accessing the timer status register satisfies the first condition required to clear the status bits. The remaining step is to access the register corresponding to the status bit. Address Timer status (TSR) $002E bit 7 IC1F bit 6 IC2F bit 5 OC1F bit 4 bit 3 bit 2 bit 1 0 bit 0 State on reset Freescale Semiconductor, Inc... TOF TCAP1 TCAP2 OC2F Undefined IC1F -- Input capture 1 flag This bit is set when the selected polarity of edge is detected by the input capture edge detector 1 at TCAP1; an input capture interrupt will be generated, if IC1IE is set. IC1F is cleared by reading the TSR and then the input capture 1 low register ($0021). 1 (set) - A valid input capture has occurred. No input capture has occurred. 6 0 (clear) - IC2F -- Input capture 2 flag This bit is set when the selected polarity of edge is detected by the input capture edge detector 2 at TCAP2; an input capture interrupt will be generated if IC2IE is set. IC2F is cleared by reading the TSR and then the input capture 2 low register ($0025). 1 (set) - A valid input capture has occurred. No input capture has occurred. 0 (clear) - OC1F -- Output compare 1 flag This bit is set when the output compare register 1 contents match those of the free-running counter; an output compare interrupt will be generated if OC1IE is set. OC1F is cleared by reading the TSR and then the output compare 1 low register ($0023). 1 (set) - A valid output compare has occurred. No output compare has occurred. 0 (clear) - TOF -- Timer overflow status flag This bit is set when the free-running counter overflows from $FFFF to $0000; a timer overflow interrupt will occur if TOIE is set. TOF is cleared by reading the TSR and the counter low register ($0029). 1 (set) - Timer overflow has occurred. No timer overflow has occurred. 0 (clear) - TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com 16-BIT PROGRAMMABLE TIMER MOTOROLA 6-7 Freescale Semiconductor, Inc. When using the timer overflow function and reading the free-running counter at random times to measure an elapsed time, a problem may occur whereby the timer overflow flag is unintentionally cleared if: 1 2 The timer status register is read or written when TOF is set, and The LSB of the free-running counter is read, but not for the purpose of servicing the flag. Freescale Semiconductor, Inc... Reading the alternate counter register instead of the counter register will avoid this potential problem. TCAP1 -- Timer capture 1 status flag This bit reflects the status of the timer capture 1 input. TCAP2 -- Timer capture 2 status flag This bit reflects the status of the timer capture 2 input. OC2F -- Output compare 2 flag This bit is set when the output compare register 2 contents match those of the free-running counter; an output compare interrupt will be generated if OC2IE is set. OC2F is cleared by reading the TSR and then the output compare 2 low register ($0027). 1 (set) - A valid output compare has occurred. No output compare has occurred. 6 0 (clear) - TPG MOTOROLA 6-8 For More Information On This Product, Go to: www.freescale.com 16-BIT PROGRAMMABLE TIMER MC68HC05F32 Freescale Semiconductor, Inc. 6.3 Input capture `Input capture' is a technique whereby an external signal is used to trigger a read of the free running counter. In this way it is possible to relate the timing of an external signal to the internal counter value, and hence to elapsed time. There are two input capture registers: input capture register 1 (ICR1) and input capture register 2 (ICR2). There are two input capture interrupt enable bits (IC1IE and IC2IE). Freescale Semiconductor, Inc... 6.3.1 Input capture register 1 (ICR1) Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset Undefined Undefined 6 Input capture 1 high (ICR1H) Input capture 1 low (ICR1L) $0020 $0021 The two 8-bit registers that make up the 16-bit input capture register 1 are read-only, and are used to latch the value of the free-running counter after the input capture edge detector circuit 1 senses a valid transition at TCAP1. The level transition that triggers the counter transfer is defined by the input edge bit (IEDG1). When an input capture 1 occurs, the corresponding flag IC1F in TSR is set. An interrupt can also accompany an input capture 1 provided the IC1IE bit in TCR1 is set. The 8 most significant bits are stored in the input capture register 1 high at $0020, the 8 least significant bits in the input capture register 1 low at $0021. The result obtained from an input capture will be one greater than the value of the free-running counter on the rising edge of the internal bus clock preceding the external transition. This delay is required for internal synchronization. Resolution is one count of the free-running counter, which is four internal bus clock cycles. The free-running counter contents are transferred to the input capture register 1 on each valid signal transition whether the input capture 1 flag (IC1F) is set or clear. The input capture register 1 always contains the free-running counter value that corresponds to the most recent input capture 1. After a read of the input capture register 1 MSB ($0020), the counter transfer is inhibited until the LSB ($0021) is also read. This characteristic causes the time used in the input capture software routine and its interaction with the main program to determine the minimum pulse period. A read of the input capture register 1 LSB ($0021) does not inhibit the free-running counter transfer since the two actions occur on opposite edges of the internal bus clock. Reset does not affect the contents of the input capture register 1, except when exiting STOP mode (see Section 6.5). TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com 16-BIT PROGRAMMABLE TIMER MOTOROLA 6-9 Freescale Semiconductor, Inc. 6.3.2 Input capture register 2 (ICR2) Address Input capture 2 high (ICR2H) Input capture 2 low (ICR2L) $0024 $0025 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset Undefined Undefined Freescale Semiconductor, Inc... 6 The two 8-bit registers that make up the 16-bit input capture register 2 are read-only, and are used to latch the value of the free-running counter after the input capture edge detector circuit 2 senses a valid transition at pin TCAP2. When an input capture 2 occurs, the corresponding flag IC2F in TSR is set. An interrupt can also accompany an input capture 2 provided the IC2IE bit in TCR1 is set. The 8 most significant bits are stored in the input capture 2 high register at $0024, the 8 least significant bits in the input capture 2 low register at $0025. The result obtained from an input capture will be one greater than the value of the free-running counter on the rising edge of the internal bus clock preceding the external transition. This delay is required for internal synchronization. Resolution is one count of the free-running counter, which is four internal bus clock cycles. The free-running counter contents are transferred to the input capture register 2 on each valid signal transition whether the input capture 2 flag (IC2F) is set or clear. The input capture register 2 always contains the free-running counter value that corresponds to the most recent input capture 2. After a read of the input capture register 2 MSB ($0024), the counter transfer is inhibited until the LSB ($0025) is also read. This characteristic causes the time used in the input capture software routine and its interaction with the main program to determine the minimum pulse period. A read of the input capture register 2 LSB ($0024) does not inhibit the free-running counter transfer since the two actions occur on opposite edges of the internal bus clock. Reset does not affect the contents of the input capture register 2, except when exiting STOP mode (see Section 6.5). TPG MOTOROLA 6-10 For More Information On This Product, Go to: www.freescale.com 16-BIT PROGRAMMABLE TIMER MC68HC05F32 Freescale Semiconductor, Inc. 6.4 Output compare `Output compare' is a technique which may be used, for example, to generate an output waveform, or to signal when a specific time period has elapsed, by presetting the output compare register to the appropriate value. There are two output compare registers: output compare register 1 (OCR1) and output compare register 2 (OCR2). There are two output compare interrupt enable bits (OC1IE and OC2IE). Freescale Semiconductor, Inc... 6.4.1 Output compare register 1 (OCR1) Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset Undefined Undefined 6 Output compare 1 high (OCR1H) Output compare 1 low (OCR1L) $0022 $0023 The 16-bit output compare register 1 is made up of two 8-bit registers at locations $0022 (MSB) and $0023 (LSB). The contents of the output compare register 1 are compared with the contents of the free-running counter continually and, if a match is found, the corresponding output compare flag (OC1F) in the timer status register is set. If the timer compare output enable bit (CO1E) is set, the output level (OLVL1) is transferred to pin TCMP1. The output compare register 1 values and the output level bit should be changed after each successful comparison to establish a new elapsed timeout. An interrupt can also accompany a successful output compare provided the corresponding interrupt enable bit (OC1IE) is set. (The free-running counter is updated every four internal bus clock cycles.) After a processor write cycle to the output compare register 1 containing the MSB ($0022), the output compare function is inhibited until the LSB ($0023) is also written. The user must write both bytes (locations) if the MSB is written first. A write made only to the LSB ($0023) will not inhibit the compare 1 function. The processor can write to either byte of the output compare register 1 without affecting the other byte. The output level (OLVL1) bit is clocked to the output level register and hence to the TCMP1 pin whether the output compare flag 1 (OC1F) is set or clear. The minimum time required to update the output compare register 1 is a function of the program rather than the internal hardware. Because the output compare flag 1 and the output compare register 1 are not defined at power on, and not affected by reset, care must be taken when initializing output compare functions with software. The following procedure is recommended: - - - Write to output compare 1 high to inhibit further compares; Read the timer status register to clear OC1F (if set); Write to output compare 1 low to enable the output compare 1 function. The purpose of this procedure is to prevent the OC1F bit from being set between the time it is read and the write to the corresponding output compare register. TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com 16-BIT PROGRAMMABLE TIMER MOTOROLA 6-11 Freescale Semiconductor, Inc. All bits of the output compare register are readable and writable and are not altered by the timer hardware or reset. If the compare function is not needed, the two bytes of the output compare register can be used as storage locations. 6.4.2 Output compare register 2 (OCR2) Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset Undefined Undefined Freescale Semiconductor, Inc... Output compare 2 high (OCR2H) Output compare 2 low (OCR2L) $0026 $0027 6 The 16-bit output compare register 2 is made up of two 8-bit registers at locations $0026 (MSB) and $0027 (LSB). The contents of the output compare register 2 are compared with the contents of the free-running counter continually and, if a match is found, the corresponding output compare flag (OC2F) in the timer status register is set. If the timer compare 2 output enable bit (CO2E) is set, the output level (OLVL2) is transferred to pin TCMP2. The output compare register 2 values and the output level bit should be changed after each successful comparison to establish a new elapsed timeout. An interrupt can also accompany a successful output compare provided the corresponding interrupt enable bit (OC2IE) is set. (The free-running counter is updated every four internal bus clock cycles.) After a processor write cycle to the output compare register 2 containing the MSB ($0026), the output compare function is inhibited until the LSB ($0027) is also written. The user must write both bytes (locations) if the MSB is written first. A write made only to the LSB ($0027) will not inhibit the compare 2 function. The processor can write to either byte of the output compare register 2 without affecting the other byte. The output level (OLVL2) bit is clocked to the output level register and hence to the TCMP2 pin whether the output compare 2 flag (OC2F) is set or clear. The minimum time required to update the output compare register 2 is a function of the program rather than the internal hardware. Because the output compare 2 flag and the output compare register 2 are not defined at power on, and not affected by reset, care must be taken when initializing output compare functions with software. The following procedure is recommended: - - - Write to output compare 2 high to inhibit further compares; Read the timer status register to clear OC2F (if set); Write to output compare 2 low to enable the output compare 2 function. The purpose of this procedure is to prevent the OC2F bit from being set between the time it is read and the write to the corresponding output compare register. All bits of the output compare register are readable and writable and are not altered by the timer hardware or reset. If the compare function is not needed, the two bytes of the output compare register can be used as storage locations. TPG MOTOROLA 6-12 For More Information On This Product, Go to: www.freescale.com 16-BIT PROGRAMMABLE TIMER MC68HC05F32 Freescale Semiconductor, Inc. 6.5 Timer during STOP mode When the MCU enters STOP mode, the timer counter stops counting and remains at that particular count value until STOP mode is exited by an interrupt. If STOP mode is exited by power-on or external reset, the counter is forced to $FFFC but if it is exited by external interrupt (IRQ) then the counter resumes from its stopped value. Another feature of the programmable timer is that if at least one valid input capture edge occurs at one of the TCAP pins while in STOP mode, the corresponding input capture detect circuitry is armed. This action does not wake the MCU or set any timer flags, but when the MCU does wake-up there will be an active input capture flag (and data) from that first valid edge which occurred during STOP mode. If STOP mode is exited by an external reset then no such input capture flag or data action takes place even if there was a valid input capture edge (at one of the TCAP pins) during STOP mode. Freescale Semiconductor, Inc... 6 6.6 Timer during WAIT mode During WAIT mode, the CPU clock halts but timer1 keeps running. Timer2 is disabled, if bit 7 (WTLCDO) of the LCD control register is set, however, if it is cleared, timer2 remains active. If interrupts are enabled, a timer interrupt will cause the processor to exit WAIT mode. 6.7 Timer state diagrams The relationships between the internal clock signals, the counter contents and the status of the flag bits are shown in the following figures. It should be noted that the signals labelled `internal' (processor clock, timer clocks and reset) are not available to the user. TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com 16-BIT PROGRAMMABLE TIMER MOTOROLA 6-13 Freescale Semiconductor, Inc. Internal processor clock Internal reset Internal timer clocks Freescale Semiconductor, Inc... T00 T01 T10 T11 $FFFC $FFFD $FFFE $FFFF 6 Note: 16-bit counter External reset or end of POR The counter and timer control registers are the only ones affected by power-on or external reset. Figure 6-2 Timer state timing diagram for reset Internal processor clock Internal timer clocks T00 T01 T10 T11 $F123 $F124 $F125 $F126 16-bit counter Input edge Internal capture latch Input capture register Input capture flag } $???? } } } $F124 Note: If the input edge occurs in the shaded area from one timer state T10 to the next timer state T10, then the input capture flag will be set during the next T11 state. Figure 6-3 Timer state timing diagram for input capture TPG MOTOROLA 6-14 For More Information On This Product, Go to: www.freescale.com 16-BIT PROGRAMMABLE TIMER MC68HC05F32 Freescale Semiconductor, Inc. Internal processor clock Internal timer clocks T00 T01 T10 T11 $F456 (Note 1) Freescale Semiconductor, Inc... 16-bit counter Output compare register Compare register latch Output compare flag and TCMP1,2 Note: 1 2 $F457 $F458 $F459 CPU writes $F457 (Note 1) $F457 6 (Note 2) The CPU write to the compare registers may take place at any time, but a compare only occurs at timer state T01. Thus a four cycle difference may exist between the write to the compare register and the actual compare. The output compare flag is set at the timer state T11 that follows the comparison match ($F457 in this example). Figure 6-4 Timer state timing diagram for output compare Internal processor clock Internal timer clocks T00 T01 T10 T11 $FFFF $0000 $0001 $0002 16-bit counter Timer overflow flag Note: The timer overflow flag is set at timer state T11 (transition of counter from $FFFF to $0000). It is cleared by a read of the timer status register during the internal processor clock high time, followed by a read of the counter low register. Figure 6-5 Timer state timing diagram for timer overflow TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com 16-BIT PROGRAMMABLE TIMER MOTOROLA 6-15 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... 6 THIS PAGE LEFT BLANK INTENTIONALLY TPG MOTOROLA 6-16 For More Information On This Product, Go to: www.freescale.com 16-BIT PROGRAMMABLE TIMER MC68HC05F32 Freescale Semiconductor, Inc. 7 DTMF/MELODY GENERATOR 7.1 Introduction Freescale Semiconductor, Inc... The DTMF/melody generator (DMG) is a multi-functional tone generator built into the MC68HC05F32 MCU which supports DTMF dialling, melody-on-hold and pacifier tone functions. 7 7.1.1 * * * * * * * * Features 4 row and 4 column frequencies for DTMF dialling 24 row and 24 column frequencies for dual tone melody 28 frequencies for pacifier tone to acknowledge button pressed for pulse dialling Power saving mechanism for output disable condition 3.579MHz/2 operation 6-bit D/A converter and 28 time steps for sine wave generation Sine wave or square wave selectable output for melody (or DTMF) Single or dual tone capability for melody (or DTMF) TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com DTMF/MELODY GENERATOR MOTOROLA 7-1 Freescale Semiconductor, Inc. 7.2 Functional description As shown in Figure 7-1, the DMG consists of 2 tone generation paths (the column and row paths). One path generates the row tone and the other the column tone, whose frequencies are determined by the values in the frequency control registers FCR and FCC respectively. The tones allowed at the TNO output are single/dual sine/square wave tones of DTMF and melody frequencies, whereas at the TNX output, only single square wave tones are allowed. The method of tone generation for the two paths is almost the same, and is described as follows. To generate a sine wave tone with programmable frequency in a path, the internal clock (i.e. the 3.58MHz/2) is first divided by a frequency divider according to a number on the register (FCR or FCC). The output of the divider is a periodic pulse train whose frequency is the sampling rate of the desired `staircase sine wave'. This pulse train, in turn, clocks a divide-by-28 binary counter (PLA scanner) whose 28 decoded outputs scan sequentially 28 memory locations of a 28x6 sine wave generator (PLA) in 28 time steps (M). The six resulting digital sine wave bits are then fed separately to a 6-bit resistor ladder to produce a current signal. The method for generating a square wave tone in a path is similar to that of a sine wave tone except that only the most significant bit of a sine wave PLA is fed to the 6-bit resistor ladder to produce a current signal (the other 5 least significant bits are masked by the sine/square wave select). Using this method, a square wave tone can be produced which has exactly the same frequency and phase as a sine wave tone, and uses the same frequency control register value. After obtaining the current signals from the row and column paths, the row current signal is first attenuated by 2dB. It is then summed with the column current signal, and is finally fed to an active 7 KHz low pass filter to reduce harmonic distortion (note that square wave tones are also passed through this filter). The resulting DTMF or melody signal is output through the TNO pin which is normally connected to a speech circuit. The generator provides not only DTMF and melody but also a square wave pacifier tone (ToneX). This signal is also extracted from the most significant bit of the sine wave PLA of the row path, but is not passed through the filter. The ToneX signal is output through the TNX pin which is normally connected to a loudspeaker. Freescale Semiconductor, Inc... 7 TPG MOTOROLA 7-2 For More Information On This Product, Go to: www.freescale.com DTMF/MELODY GENERATOR MC68HC05F32 Freescale Semiconductor, Inc. 3.58 MHz/2 msb Row frequency divider PLA scanner Sine wave PLA 28 x 6 bit 6 Sine/square wave select MUX lsb TNX Freescale Semiconductor, Inc... 5 6-bit resistor ladder Current summer + active low pass filter FCR register FCC register Data validator TGER TGEC MS1 MS0 TNO + 7 TNOE 5 Tristate control STOP Row frequency divider PLA scanner Sine wave PLA 28 x 6 bit 6 Sine/square wave select 6 6-bit resistor ladder High group pre-emphasis Figure 7-1 DTMF/melody generator (DMG) block diagram TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com DTMF/MELODY GENERATOR MOTOROLA 7-3 Freescale Semiconductor, Inc. 7.3 DMG registers The DMG has two registers (row frequency control register and column frequency control register) for row and column frequency selection respectively, and one register (tone control register) for tone output control and mode selection. 7.3.1 Row and column frequency control registers Address bit 7 0 bit 6 0 bit 5 0 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset Freescale Semiconductor, Inc... Row frequency control register (FCR) $000D FCR4 FCR3 FCR2 FCR1 FCR0 undefined 7 Column frequency control register (FCC) Address $000E bit 7 0 bit 6 0 bit 5 0 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset FCC4 FCC3 FCC2 FCC1 FCC0 undefined FCR4-FCR0 and FCC4-FCC0 control the frequency of the tone signals on the row and the column paths respectively. The row and column paths are not exactly identical owing to the presence of the high group pre-emphasis in the column path. In order to avoid the entry of the row DTMF tone values to the column, and vice versa, the above cases are treated as illegal. The data validator will disable all outputs when an illegal value is detected. The bit description for DTMF and melody tone generation are shown in Table 7-1 and Table 7-2 respectively. It is the user's responsibility to ensure good programming practice by initialising all registers to contain legal values for the desired function. 7.3.2 Tone control register (TNCR) This register controls the internal configuration and tone output timing of the DTMF/melody generator. Address Tone control register (TNCR) $000F bit 7 MS1 bit 6 MS0 bit 5 bit 4 bit 3 0 bit 2 0 bit 1 0 bit 0 State on reset TGER TGEC TNOE 0000 0000 MS1, MS0 -- Melody select for operation The MS0 and MS1 bits control the mode of operation of the DTMF/melody generator. There are sine wave, square wave 1, square wave 2 and square wave 3 modes. They are specified as shown in Table 7-3. TPG MOTOROLA 7-4 For More Information On This Product, Go to: www.freescale.com DTMF/MELODY GENERATOR MC68HC05F32 Freescale Semiconductor, Inc. When square wave 2 or square wave 3 mode is selected, the TNX pin is activated. The idle state for TNX is a logic high. The final state of the TNX pin is still dependent on the values of TGER, TGEC (see Table 7-4), FCR and FCC bits (when illegal values are input). The state of the TNO pin depends on the value of the TNOE bit. After a RESET, the TNOE is cleared and the TNO pin is tristate. When TNOE is set, the TNO output is activated. If the TGER and TGEC bits are held low and TNOE is set, the dc offset of VDD/2 appears at TNO pin. In STOP mode, the TNX pin is high and the TNO pin is tristate. When both MS1 and MS0 are set (square wave 3), the generator can generate both single tone melody at the column path, and ToneX at the row path simultaneously. TGER -- Tone generator enable row path 1 (set) - Row path on Row path off Freescale Semiconductor, Inc... 0 (clear) - 7 TGEC -- Tone generator enable column path 1 (set) - Column path on Column path off 0 (clear) - TNOE -- Tone output enable 1 (set) - TNO on TNO off 0 (clear) - Table 7-1 Bit description for DTMF generation Standard frequency (Hz) 697.0 770.0 852.0 941.0 1209.0 1336.0 1477.0 1633.0 FCR register $00 $01 $02 $03 FCC register Tone fR1 fR2 fR3 fR4 fC1 fC2 fC3 fC4 Tone output Frequency frequency (Hz) deviation 694.8 770.1 854.2 940.0 1206.0 1331.7 1486.5 1639.0 -0.32 0.02 0.03 -0.11 -0.244 -0.324 0.645 0.367 $10 $11 $12 $13 Note: The legal values in the FCR register column are illegal to the FCC register, and vice versa. An input of illegal values to these registers will produce a high at TNX output and VDD /2 at TNO output (TNOE = 1) TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com DTMF/MELODY GENERATOR MOTOROLA 7-5 Freescale Semiconductor, Inc. . Table 7-2 Bit description for melody generator Standard Tone output Frequency frequency frequency deviation (Hz) (Hz) (%) 622.3 620.6 -0.28 659.3 659.0 -0.05 698.5 694.8 -0.53 740.0 743.3 0.44 784.0 779.5 -0.57 830.6 830.1 -0.06 880.0 875.6 -0.50 932.0 926.4 -0.64 987.8 983.4 -0.45 1046.5 1047.9 0.13 1108.7 1102.1 -0.60 1174.7 1183.7 0.77 1244.5 1253.3 0.71 1318.5 1331.7 1.00 1396.9 1389.6 -0.52 1480.0 1486.5 0.44 1568.0 1559.0 -0.57 1661.2 1682.1 1.26 1760.0 1775.6 0.89 1864.7 1880.0 0.82 1975.5 1997.5 1.11 2093.0 2062.0 -1.49 2217.5 2204.2 -0.60 2349.3 2367.4 0.771 FCR/FCC register $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F $14 $15 $16 $17 $18 $19 $1A $1B $1C $1D $1E $1F Tone D#5 E5 F5 F#5 G5 G#5 A5 A#5 B5 C6 C#6 D6 D#6 E6 F6 F#6 G6 G#6 A6 A#6 B6 C7 C#7 D7 Freescale Semiconductor, Inc... 7 Table 7-3 Mode of operation for DMG MS1 0 0 1 1 MS0 0 1 0 1 Mode sine wave square wave 1 square wave 2 square wave 3 TNX output high high row frequency row frequency TNO output sine wave row and column frequency square wave row and column frequency square wave row and column frequency square wave column frequency TPG MOTOROLA 7-6 For More Information On This Product, Go to: www.freescale.com DTMF/MELODY GENERATOR MC68HC05F32 Freescale Semiconductor, Inc. TGER, TGEC -- Tone generation enable for row and column paths When both bits are held low, the DMG is disabled by forcing the two frequency counters and the two PLA scanning counters to their reset states. The DMG should then consume zero dynamic power, if the TNOE bit is also cleared. When a TGE bit for a path is held high (provided that the value in the frequency control register for that path is legal), the generator is enabled. All the counters associated with that path are then run from their reset states. The reset state of a frequency counter defines the time=0 state of the time step, whereas at their reset state, the PLA scanning counters, scanning the memory location, contain the dc values of the staircase sine wave. In DTMF dialling, the row and column tone values are first entered to the FCR and FCC registers. The TGER and TGEC bits are then set or reset simultaneously to achieve dual tone multiple frequency. Similarly, in melody generation, one path is chosen as the high part, and the other as the low part. The TGER and TGEC bits are then set and reset according to the rhythm required by the musical piece. One can exhibit only single tone melody by disabling either TGER or TGEC permanently. The DTMF column and row frequency tones can also be output separately for testing by enabling just the one path. Freescale Semiconductor, Inc... 7 Table 7-4 Effect of tone generation on DMG Column Path off active off active TGER 0 0 1 1 TGEC Row Path 0 1 0 1 off off active active 7.4 Operation of the DMG The DMG is recommended to be operated using the following procedures: To operate melody generation, the choice of sine wave or square wave output mode is totally up to the user's taste. The sine wave melody has a sound like a flute, whereas the square wave melody possesses much richer harmonics. The required tones are selected through the FCR and FCC registers. The selected tone is output when the corresponding TGER or TGEC bit and TNOE bit are set. The FCR register should contain the value representing the tone output frequency and the FCC register should contain a value of $03 or greater to ensure the output is not blocked by the data validator. TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com DTMF/MELODY GENERATOR MOTOROLA 7-7 Freescale Semiconductor, Inc. 7.5 DMG during WAIT mode The DMG is still active during the WAIT mode. 7.6 DMG during STOP mode Freescale Semiconductor, Inc... In STOP mode the oscillator is stopped causing the DMG to cease function. 7 TPG MOTOROLA 7-8 For More Information On This Product, Go to: www.freescale.com DTMF/MELODY GENERATOR MC68HC05F32 Freescale Semiconductor, Inc. 8 LIQUID CRYSTAL DISPLAY DRIVER MODULE The LCD driver module on the MC68HC05F32 supports 40 frontplanes and 4 backplanes, allowing a maximum of 160 LCD segments. Each segment is controlled by a corresponding bit in the LCD RAM. The mode of operation is determined by the values set in the LCD control register at $1E. After reset and on leaving standby, the drivers are configured in the default duplex mode, 1/2 bias with 2 backplanes. At power-up or after reset, the ON/OFF control bits for the internal and external VLCD voltage (INTVLCD and EXTVON) are cleared, disabling the LCD drivers. Figure 8-1 shows a block diagram of the LCD system. At power-up or after reset the LCD port's control bits are cleared, which disables the LCD frontplane drivers. Freescale Semiconductor, Inc... 8 Internal data bus Internal address bus 13 8 Internal signals Control logic LCD RAM Backplane driver BP3 BP2 BP1 BP0 Segment driver Voltage generator V LCD FP17 FP0 Figure 8-1 LCD system block diagram TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com LIQUID CRYSTAL DISPLAY DRIVER MODULE MOTOROLA 8-1 Freescale Semiconductor, Inc. 8.1 LCD RAM Freescale Semiconductor, Inc... Data to be displayed on the LCD must be written into the LCD RAM. The LCD RAM is comprised of 20 bytes of RAM (in the MC68HC05F32's memory map) at $0054 - $0067. The 160 bits in the LCD RAM correspond to the 160 segments that can be driven by the frontplane/backplane drivers. Table 8-1 shows how the LCD RAM is organized. Writing a `1' to a given location will result in the corresponding display segment being activated when the EXTVON or INTVLCD bit is set. The LCD RAM is a dual port RAM that interfaces with the internal address and data buses of the MCU. It is possible to read from LCD RAM locations for scrolling purposes. Table 8-1 LCD RAM organization LCD RAM Address $54 $55 $56 $57 $58 $59 $5A $5B $5C $5D $5E $5F $60 $61 $62 $63 $64 $65 $66 $67 Data bit 7 FP1-BP3 FP3-BP3 FP5-BP3 FP7-BP3 FP9-BP3 FP11-BP3 FP13-BP3 FP15-BP3 FP17-BP3 FP19-BP3 FP21-BP3 FP23-BP3 FP25-BP3 FP27-BP3 FP29-BP3 FP31-BP3 FP33-BP3 FP35-BP3 FP37-BP3 FP39-BP3 bit 6 FP1-BP2 FP3-BP2 FP5-BP2 FP7-BP2 FP9-BP2 FP11-BP2 FP13-BP2 FP15-BP2 FP17-BP2 FP19-BP2 FP21-BP2 FP23-BP2 FP25-BP2 FP27-BP2 FP29-BP2 FP31-BP2 FP33-BP2 FP35-BP2 FP37-BP2 FP39-BP2 bit 5 FP1-BP1 FP3-BP1 FP5-BP1 FP7-BP1 FP9-BP1 FP11-BP1 FP13-BP1 FP15-BP1 FP17-BP1 FP19-BP1 FP21-BP1 FP23-BP1 FP25-BP1 FP27-BP1 FP29-BP1 FP31-BP1 FP33-BP1 FP35-BP1 FP37-BP1 FP39-BP1 bit 4 FP1-BP0 FP3-BP0 FP5-BP0 FP7-BP0 FP9-BP0 FP11-BP0 FP13-BP0 FP15-BP0 FP17-BP0 FP19-BP0 FP21-BP0 FP23-BP0 FP25-BP0 FP27-BP0 FP29-BP0 FP31-BP0 FP33-BP0 FP35-BP0 FP37-BP0 FP39-BP0 bit 3 FP0-BP3 FP2-BP3 FP4-BP3 FP6-BP3 FP8-BP3 FP10-BP3 FP12-BP3 FP14-BP3 FP16-BP3 FP18-BP3 FP20-BP3 FP22-BP3 FP24-BP3 FP26-BP3 FP28-BP3 FP30-BP3 FP32-BP3 FP34-BP3 FP36-BP3 FP38-BP3 bit 2 FP0-BP2 FP2-BP2 FP4-BP2 FP6-BP2 FP8-BP2 FP10-BP2 FP12-BP2 FP14-BP2 FP16-BP2 FP18-BP2 FP20-BP2 FP22-BP2 FP24-BP2 FP26-BP2 FP28-BP2 FP30-BP2 FP32-BP2 FP34-BP2 FP36-BP2 FP38-BP2 bit 1 FP0-BP1 FP2-BP1 FP4-BP1 FP6-BP1 FP8-BP1 FP10-BP1 FP12-BP1 FP14-BP1 FP16-BP1 FP18-BP1 FP20-BP1 FP22-BP1 FP24-BP1 FP26-BP1 FP28-BP1 FP30-BP1 FP32-BP1 FP34-BP1 FP36-BP1 FP38-BP1 bit 0 FP0-BP0 FP2-BP0 FP4-BP0 FP6-BP0 FP8-BP0 FP10-BP0 FP12-BP0 FP14-BP0 FP16-BP0 FP18-BP0 FP20-BP0 FP22-BP0 FP24-BP0 FP26-BP0 FP28-BP0 FP30-BP0 FP32-BP0 FP34-BP0 FP36-BP0 FP38-BP0 8 TPG MOTOROLA 8-2 LIQUID CRYSTAL DISPLAY DRIVER MODULE For More Information On This Product, Go to: www.freescale.com MC68HC05F32 Freescale Semiconductor, Inc. 8.2 LCD operation The LCD driver module can operate in four modes providing different multiplex ratios and number of backplanes as follows: * * * * 1/2 bias, 2 backplanes 1/3 bias, 2 backplanes 1/3 bias, 3 backplanes 1/4 bias, 4 backplanes Freescale Semiconductor, Inc... The operating mode is selected at power on using the multiplex ratio bits (MUX3 and MUX4) in the LCD control register as shown in Table 8-4. It is recommended that the EXTVON and INTVLCD bits in the LCD register are not set (display is disabled) until the multiplex rate is selected. The voltage levels required for the different multiplex rates are generated internally by a resistive divider chain between VLCD and VSS. The 2-way multiplex with 1/3 bias and the three and four-way multiplex options require four voltage levels, whereas the two-way multiplex with 1/2 bias needs only three levels. Resistors R1, R2 and R3 are valued at 20k 40%. Figure 8-2 shows the resistive divider chain network that is used to produce the various LCD waveforms outlined in Section 8.3. The LCD drivers can operate with an external VLCD supply when EXTVON = 1, or with an internally generated LCD voltage when INTVLCD = 1. The EXTVON option is useful when a display with particular thresholds is being used. The LCD controller is enabled if the EXTVON bit or the INTVLCD bit is set. Table 8-2 shows the different modes of operation depending on the bits EXTVON and INTVLCD of the LCD control register. 8 Table 8-2 LCD controller operating modes LCD Internal voltage controller generator off off on on on off on on Resistor chain connected with -- internal VLCD VLCD pin both (for test) EXTVON INTVLCD 0 0 1 1 0 1 0 1 Note: Note: The external voltage VLCD may not exceed the positive power supply voltage, VDD. If both bits INTVLCD and EXTVON are set, an externally applied voltage source can cause damage to the LCD drivers. . TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com LIQUID CRYSTAL DISPLAY DRIVER MODULE MOTOROLA 8-3 Freescale Semiconductor, Inc. VLCD EXTVON V LCD R3 V2 2 BP, 1/2 Bias R2 V1 R1 int. gen. VLCD INTVLCD Freescale Semiconductor, Inc... VSS Figure 8-2 Voltage level selection 8 8.3 Timing signals and LCD voltage waveforms The LCD timing signals are all derived from the main system clock. The frame rate will be fOSC/216, therefore, if fOSC = 3.579 MHz, the frame rate will be 54.6 Hz for two and four-way multiplexing and 72.8 Hz for three-way multiplexing (see Table 8-4). An extra divide-by-two stage can be included in the LCD clock generator by setting FDISP in the LCD register. This will result in the frame rate being halved. For example, when three-way multiplexing is used, a frame rate of 36.4 Hz instead of 72.8 Hz can be obtained. See Section 8.4. Figure 8-3 to Figure 8-6 show the backplane waveforms and some examples of frontplane waveforms for each of the operating modes. The backplane waveforms are continuous and repetitive (every frame); they are fixed within each operating mode and are not affected by the data in the LCD RAM. The frontplane waveforms are dependent on the LCD segments to be driven as defined in the LCD RAM. Each `on' segment must have a differential driving voltage (BP-FP) applied to it once in each frame; the LCD driver module hardware uses the data in the LCD RAM to construct the frontplane waveform to meet this criterion. TPG MOTOROLA 8-4 LIQUID CRYSTAL DISPLAY DRIVER MODULE For More Information On This Product, Go to: www.freescale.com MC68HC05F32 Freescale Semiconductor, Inc. V DD /VLCD BP0 V2 V0 V DD /VLCD Freescale Semiconductor, Inc... BP1 V2 V0 ON OFF V DD /VLCD FPx, example 1 1 Frame V2 V0 V DD /VLCD FPx, example 2 V2 V0 8 V DD /VLCD FPx, example 3 V2 V0 V DD /VLCD FPx, example 4 V2 V0 Note: In this mode V1=V2 Figure 8-3 LCD waveform with 2 backplanes, 1/2 bias TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com LIQUID CRYSTAL DISPLAY DRIVER MODULE MOTOROLA 8-5 Freescale Semiconductor, Inc. V DD /VLCD BP0 V2 V1 V0 V DD /VLCD Freescale Semiconductor, Inc... BP1 V2 V1 V0 ON OFF 1 Frame FPx, example 1 V2 V1 8 V DD /VLCD FPx, example 2 V2 V1 V0 V DD /VLCD FPx, example 3 V2 V1 V0 V DD /VLCD V2 FPx, example 4 V1 V0 Figure 8-4 LCD waveform with 2 backplanes, 1/3 bias TPG MOTOROLA 8-6 LIQUID CRYSTAL DISPLAY DRIVER MODULE For More Information On This Product, Go to: www.freescale.com MC68HC05F32 Freescale Semiconductor, Inc. V DD /VLCD V2 BP0 V1 V0 Freescale Semiconductor, Inc... V DD /VLCD BP1 V2 V1 V0 V DD /VLCD V2 ON OFF 1 Frame BP2 V1 V0 8 V DD /VLCD V2 FPx, example 1 V1 V0 V DD /VLCD V2 FPx, example 2 V1 V0 V DD /VLCD V2 FPx, example 3 V1 V0 Figure 8-5 LCD waveform with 3 backplanes TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com LIQUID CRYSTAL DISPLAY DRIVER MODULE MOTOROLA 8-7 Freescale Semiconductor, Inc. V DD /VLCD BP0 V2 V1 V0 V DD /VLCD BP1 V2 V1 V0 V DD /VLCD Freescale Semiconductor, Inc... ON OFF 1 Frame BP2 V2 V1 V0 V DD /VLCD V2 8 BP3 V1 V0 V DD /VLCD FPx, example 1 V2 V1 V0 V DD /VLCD V2 FPx, example 2 V1 V0 V DD /VLCD V2 FPx, example 3 V1 V0 Figure 8-6 LCD waveform with 4 backplanes TPG MOTOROLA 8-8 LIQUID CRYSTAL DISPLAY DRIVER MODULE For More Information On This Product, Go to: www.freescale.com MC68HC05F32 Freescale Semiconductor, Inc. 8.4 LCD control register (LCD) Address LCD control register (LCD) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset $001E WTLCDO FSEL1 FSEL0 INTVLCD FDISP MUX4 MUX3 EXTVON 0000 0000 WTLCDO -- WAIT mode LCD only 1 (set) - The SPI, the SCI, the second 16-bit timer and the A/D converter are turned off in WAIT mode. The SPI, the SCI, the second 16-bit timer and the A/D converter remain active during WAIT mode. Freescale Semiconductor, Inc... 0 (clear) - If this bit is set, the SPI, the SCI, the second 16-bit timer and the A/D converter are turned off in WAIT mode, reducing the power consumption, as only the core timer, the first 16-bit timer (timerA), the DMG and the LCD controller remain active. FSEL1, FSEL0 -- LCD operation frequency These bits select the LCD operation frequency according to Table 8-3. The frequency shown in the right columns are calculated for an external frequency of 3.579 MHz. 8 Table 8-3 Frequency selection Framefrequency Frame frequency (2, 4 backplanes) (3 backplanes) FOSC /216 4F OSC /(3X216 ) 15 FOSC /2 4F OSC /(3X215 ) 14 FOSC /2 4F OSC /(3X214 ) 9 FOSC /2 4F OSC /(3X29) Frequency for 2,4 backplanes 54.6 Hz 109.2 Hz 218.4 Hz 6990 Hz Frequency for 3 backplanes 72.8 Hz 145.6 Hz 291.3 Hz 9320 Hz FSEL1: FSEL0 00 10 01 11 INTVLCD -- Internal voltage generator ON/OFF 1 (set) - The display is on and an internal voltage generator is activated. The internal voltage generator is turned off. 0 (clear) - When the INTVLCD bit is set, the display controller is on and an internal voltage generator is activated and connected to the resistor chain (VLCD = 3V approx., if VDD > 3V). See Table 8-2. TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com LIQUID CRYSTAL DISPLAY DRIVER MODULE MOTOROLA 8-9 Freescale Semiconductor, Inc. FDISP -- Display frequency 1 (set) - Extra divide by two stage is included in the LCD clock generator when this bit is set, giving a reduced frame rate. Default frame rate is used. 0 (clear) - For example, in the 3-way multiplexing mode, a frame rate of 36.8 Hz instead of 72.8 Hz can be achieved. MUX4, MUX3 -- Multiplex ratio These two bits select the multiplex ratio to be 2, 3 or 4 backplanes. See Table 8-4. Table 8-4 Multiplex ratio/backplane selection MUX4 0 0 1 1 MUX3 0 1 0 1 Backplanes 2 3 4 2 Bias 1/2 1/3 1/3 1/3 Frequency 54.6 Hz 72.8 Hz 54.6 Hz 54.6 Hz Freescale Semiconductor, Inc... 8 1 (set) - EXTVON -- External LCD voltage ON/OFF External LCD voltage is connected. External LCD voltage is disconnected. 0 (clear) - Clearing this bit disconnects the voltage generator resistor chain from the external VLCD. See Table 8-2. 8.5 LCD during WAIT mode The LCD drivers function normally during WAIT mode and will keep the display active if the EXTVON bit or the INTVLCD bit is set. 8.6 LCD during STOP mode During STOP mode the LCD controller is disabled. The driver outputs are discharged by the resistor chain. TPG MOTOROLA 8-10 LIQUID CRYSTAL DISPLAY DRIVER MODULE For More Information On This Product, Go to: www.freescale.com MC68HC05F32 Freescale Semiconductor, Inc. 9 A/D CONVERTER The analog to digital converter system consists of a 12-channel, multiplexed input to a successive approximation A/D converter. Eight of the A/D input channels are connected to pins PD0-PD7 and the particular input to be selected is determined by the setting/clearing of the CHx bits in the A/D status/control register at $4F. A further four channels are available internally for test purposes. In addition to the A/D status/control register (ADSCR) there is one 8-bit result data register at address $4E. The A/D converter is ratiometric and a dedicated pin, VREFH, is used to supply the upper reference voltage level of each analog input. The lower voltage reference point, VREFL, is internally connected to the AVSS pin. An input voltage equal to or greater than VRH converts to $FF (full scale) with no overflow indication. For ratiometric conversions, the source of each analog input should use VREFH as the supply voltage and be referenced to AVSS. The A/D converter can operate from either the bus clock or an internal RC type oscillator. The internal RC type oscillator is activated by the ADRC bit in the A/D status/control register (ADRC) and can be used to give a sufficiently high clock rate to the A/D converter when the bus speed is too low to provide accurate results (see Section 9.2.1). When the A/D converter is not being used it can be disconnected using the ADON bit in the ADSCR register, in order to save power (see Section 9.2.1). Freescale Semiconductor, Inc... 9 9.1 A/D converter operation The A/D converter consists of an analog multiplexer, an 8-bit digital-to-analog capacitor array, a comparator and a successive approximation register (SAR). See Figure 9-1. The A/D reference inputs is applied to a precision internal digital-to-analog converter. Control logic drives this D/A converter and the analog output is successively compared with the analog input sampled at the beginning of the conversion. The conversion is monotonic with no missing codes. The result of each successive comparison is stored in the SAR and, when the conversion is complete, the contents of the SAR are transferred to the read-only result data register ($4E), and the conversion complete flag, COCO, is set in the A/D status/control register ($4F). TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com A/D CONVERTER MOTOROLA 9-1 Freescale Semiconductor, Inc. PD7/AN7 PD6/AN6 PD5/AN5 PD4/AN4 PD3/AN3 PD2/AN2 PD1/AN1 PD0/AN0 8-bit capacitive DAC with sample and hold VRH VRL = AVSS V RH Analog MUX (Channel assignment) Successive approximation register and control Result Freescale Semiconductor, Inc... A/D status/control register (ADSCR) $4F CH0 CH1 CH2 CH3 0 ADON ADRC COCO (VRH +V RL )/2 V RL = AV SS 9 A/D result register (ADDATA) $4E Figure 9-1 A/D converter block diagram Caution: Any write to the A/D status/control register will abort the current conversion, reset the conversion complete flag and start a new conversion on the selected channel. At power-on or external reset, both the ADRC and ADON bits are cleared, thus the A/D is disabled. TPG MOTOROLA 9-2 For More Information On This Product, Go to: www.freescale.com A/D CONVERTER MC68HC05F32 Freescale Semiconductor, Inc. 9.2 9.2.1 A/D registers A/D status/control register (ADSCR) Address A/D status/control (ADSCR) bit 7 bit 6 bit 5 bit 4 0 bit 3 CH3 bit 2 CH2 bit 1 CH1 CH0 bit 0 State on reset $004F COCO ADRC ADON 0000 0000 Freescale Semiconductor, Inc... COCO -- Conversion complete flag Each channel conversion takes 32 clock cycles at fOP, where fOP is equal to or greater than 1MHz. 1 (set) - COCO flag is set each time a conversion is complete, allowing the new result to be read from the A/D result data register ($4E). The converter then starts a new conversion. COCO is cleared by reading the result data register or writing to the status/control register. 0 (clear) - Reset clears the COCO flag. ADRC -- A/D RC oscillator control If the MCU bus frequency is less than 1MHz, an internal RC oscillator must be used for the A/D conversion clock. This selection is made by setting the ADRC bit in ADSCR. The ADRC bit allows the user to control the A/D RC oscillator. 1 (set) - The A/D RC oscillator is turned on and, if ADON is set, the A/D runs from the internal RC oscillator clock (see Table 9-1). The A/D RC oscillator is turned off and, if ADON is set, the A/D runs from the CPU clock. 9 0 (clear) - When the A/D RC oscillator is turned on, it takes a time tRCON to stabilize (see Table 16-5). During this time A/D conversion results may be inaccurate. Table 9-1 A/D clock selection RC A/D Comments oscillator converter OFF OFF A/D switched off. OFF ON A/D using CPU clock. ON OFF Allows the RC oscillator to stabilize. ON ON A/D using RC oscillator clock. ADRC 0 0 1 1 ADON 0 1 0 1 TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com A/D CONVERTER MOTOROLA 9-3 Freescale Semiconductor, Inc. When the internal RC oscillator is being used as the conversion clock, the following limitations apply. 1) Due to the frequency tolerance of the RC oscillator and its asynchronism with regard to the MCU bus clock, the conversion complete flag (COCO) must be used to determine when a conversion sequence has been completed. 2) The conversion process runs at the nominal 1.5MHz rate but the conversion results must be transferred to the MCU result registers synchronously with the MCU bus clock in order that conversion time is limited to a maximum of one channel per bus clock cycle. 3) If the system clock is running faster than the RC oscillator, the RC oscillator should be switched off and the system clock used as the conversion clock. ADON -- A/D converter on The ADON bit allows the user to enable/disable the A/D converter. 1 (set) - A/D converter is switched on. A/D converter is switched off. Freescale Semiconductor, Inc... 9 0 (clear) - When the A/D converter is switched on, it takes a time tADON for the current sources to stabilize (see Table 16-5). During this time A/D conversion results may be inaccurate. Power-on or external reset will clear the ADON bit, thus disabling the A/D converter. CH3 - CH0 -- A/D channel selection The CH3-CH0 bits allow the user to determine which channel of the A/D converter multiplexer is selected (see Table 9-2). Table 9-2 A/D channel assignment CH3 0 0 0 0 0 0 0 0 1 1 1 1 CH2 0 0 0 0 1 1 1 1 1 1 1 1 CH1 0 0 1 1 0 0 1 1 0 0 1 1 CH0 0 1 0 1 0 1 0 1 0 1 0 1 Channel 0 1 2 3 4 5 6 7 8 9 10 11 Signal AD0/PD0 AD1/PD1 AD2/PD2 AD3/PD3 AD4/PD4 AD5/PD5 AD6/PD6 AD7/PD7 V REFH (V REFH +V REFL )/2 V REFL Factory test TPG MOTOROLA 9-4 For More Information On This Product, Go to: www.freescale.com A/D CONVERTER MC68HC05F32 Freescale Semiconductor, Inc. 9.2.2 A/D result data register (ADDATA) Address A/D data register $004E bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset Undefined Freescale Semiconductor, Inc... The A/D data register is a read-only register which is used to store the result of an A/D conversion. The result is loaded into the register from the SAR and the conversion complete flag (COCO) in the ADSCR register is set. Caution: Performing a digital read of port D with levels other than VDD or VSS on the pins will result in greater power dissipation during the read cycles. 9.3 A/D converter during WAIT mode The A/D converter continues to operate normally during WAIT mode. To decrease power consumption during WAIT, it is recommended that both the ADON and ADRC bits in the ADSTAT register are cleared, if the A/D converter is not being used. If the A/D converter is being used and the system clock frequency is above 1MHz, the ADRC bit should be cleared to disable the internal RC oscillator. 9 9.4 A/D converter during STOP mode In STOP mode the comparator and charge pump are turned off and the A/D converter ceases to operate. Any pending conversion is aborted. When the clock begins oscillation upon leaving the STOP mode, a finite amount of time passes before the A/D circuits stabilize enough to provide conversions to the specified accuracy. Normally, the delays built into the MC68HC05F32 are sufficient for this purpose, therefore no explicit delays need to be built into the software. 9.5 A/D analog input The external analog voltage value to be processed by the A/D converter is sampled on an internal capacitor through a resistive path, provided by input-selection switches and a sampling aperture time switch, as shown in Figure 9-2. Sampling time is limited to 12 bus clock cycles. After sampling, the analog value is stored on the capacitor and held until the end of conversion. During this hold time, the analog input is disconnected from the internal A/D system and the external voltage source sees a high impedance input. TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com A/D CONVERTER MOTOROLA 9-5 Freescale Semiconductor, Inc. The equivalent analog input during sampling is an RC low-pass filter with a minimum resistance of 50 k and a capacitance of at least 10pF. (It should be noted that these are typical values measured at room temperature). Input protection device Analog input pin (AD0-AD7) < 2pF 50k Freescale Semiconductor, Inc... + 20V - 0.7V 10 A junction leakage 10pF DAC capacitance V REFL = AVSS Note: The analog switch is closed during the 12 cycle sample time only. 9 Figure 9-2 Electrical model of an A/D input pin TPG MOTOROLA 9-6 For More Information On This Product, Go to: www.freescale.com A/D CONVERTER MC68HC05F32 Freescale Semiconductor, Inc. 10 SERIAL PERIPHERAL INTERFACE 10.1 Overview and features Freescale Semiconductor, Inc... The SPI is a synchronous interface which allows several SPI microcontrollers or SPI-type peripherals to be interconnected. In a serial peripheral interface, separate wires (signals) are required for data and clock. In the SPI format, the clock is not included in the data stream and must be furnished as a separate signal. The high-end SPI system may be configured either as a master or as a slave. Features, * * * * * * * * * * Full-duplex, 3-wire synchronous transfers Master or slave operation Master bit frequency, fOP/2 Slave bit frequency, fOP Four programmable master bit rates Programmable clock polarity and phase End-of-transmission interrupt flag Write collision flag protection Master-master mode fault protection Easy interface to simple expansion parts (PLLs, D/As, latches, display drivers, etc.) 10 TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com SERIAL PERIPHERAL INTERFACE MOTOROLA 10-1 Freescale Semiconductor, Inc. 10.2 SPI signal descriptions Four I/O pins located at port C (PC4 - PC7) are associated with the SPI data transfers. They are the serial clock (SCK), the master in/slave out data line (MISO), the master out / slave in data line (MOSI), and the active-low slave select (SS). When the SPI system is not utilized (SPE bit cleared in the serial peripheral control register), the four pins (MISO, MOSI, SCK, and SS) are configured as general-purpose I/O pins. The four SPI signals are discussed in the following paragraphs for both master mode and slave mode of operation. Freescale Semiconductor, Inc... 10.2.1 Master in slave out (MISO) The MISO line is configured as an input, in a master device, and as an output in a slave device. It is one of the two lines that transfer serial data in one direction. The MISO line of a slave device is placed in the high-impedance state if the slave is not selected. 10.2.2 Master out slave in (MOSI) The MOSI line is configured as an output in a master device, and as an input in a slave device. It is one of the two lines that transfer serial data in one direction. 10 10.2.3 Serial clock (SCK) The serial clock is used to synchronize data movement both in and out of the device through its MOSI and MISO lines. The master and slave devices are capable of exchanging a byte of information during a sequence of eight clock cycles. Since SCK is generated by the master device, this line becomes an input on a slave device. As shown in Figure 10-1, four different timing relationships may be selected by control bits CPOL and CPHA in the serial peripheral control register (SPCR). Both master and slave devices must operate with the same timing. The master device always places data on the MOSI line a half cycle before the clock edge (SCK), in order for the slave device to latch the data. Two bits (SPR0 and SPR1) in the SPI control register (SPCR) of the master device select the clock rate. In a slave device, SPR0 and SPR1 have no effect on the operation of the SPI. TPG MOTOROLA 10-2 For More Information On This Product, Go to: www.freescale.com SERIAL PERIPHERAL INTERFACE MC68HC05F32 Freescale Semiconductor, Inc. SS SS SCK (CPOL = 0, CPHA = 0) Freescale Semiconductor, Inc... SCK (CPOL = 0, CPHA = 1) SCK (CPOL = 1, CPHA = 0) SCK (CPOL = 1, CPHA = 1) MISO/ MOSI MSB 6 5 4 3 2 1 LSB 10 Internal strobe for data capture (DOD = 0) Figure 10-1 Data clock timing diagram TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com SERIAL PERIPHERAL INTERFACE MOTOROLA 10-3 Freescale Semiconductor, Inc. 10.2.4 Slave select (SS) Freescale Semiconductor, Inc... The slave select (SS) input line is used to select a slave device. It must be in the active low state prior to data transactions and must stay low for the duration of the transaction. The SS line on the master must be tied high. If it goes low, a mode fault error flag (MODF) is set in the serial peripheral status register (SPSR). When CPHA = 0, the shift clock is the logical OR of SS and SCK. In this clock phase mode, SS must go high between successive characters in an SPI message. When CPHA = 1, SS may be left low for several SPI characters. If there is only one SPI slave MCU, its SS line may be tied to VSS, provided CPHA = 1 clock modes are used. 10.3 Functional description Figure 10-2 shows a block diagram of the serial peripheral interface circuitry. When a master device transmits data to a slave device via the MOSI line, the slave device responds by sending data to the master device via the master's MISO line. This implies full duplex transmission with both data out and data in synchronized to the same clock signal. Thus, the byte transmitted is replaced by the byte received, eliminating the need for separate transmitter-empty and receiver-full status bits. A single status bit (SPIF) is used to signify that the I/O operation has been completed. The SPI is double buffered on read, but not on write. If a write is performed during data transfer, the transfer is not interrupted, and the write will be unsuccessful. This condition will cause the write collision status bit (WCOL) in the SPSR to be set. After a data byte is shifted, the SPIF flag in the SPSR is set. In master mode, the SCK pin is an output. It idles high or low, depending on the CPOL bit in the SPCR, until data is written to the shift register. Eight clocks are then generated to shift the eight bits of data, after which SCK goes idle again. In slave mode, the slave start logic receives a logic low on the SS pin and a clock input at the SCK pin, thus synchronizing the slave to the master. Data from the master is received serially via the slave MOSI line and is loaded into the 8-bit shift register. The data is then transferred, in parallel, from the 8-bit shift register to the read buffer. During a write cycle, data is written into the shift register, then the slave waits for a clock train from the master to shift the data out on the slave's MISO line. 10 TPG MOTOROLA 10-4 For More Information On This Product, Go to: www.freescale.com SERIAL PERIPHERAL INTERFACE MC68HC05F32 Freescale Semiconductor, Inc. MISO/ PC4 MOSI/ PC5 SCK/ PC6 SS/ PC7 S M msb M S Control logic S M 8-bit shift register Read data buffer lsb Internal MCU clock Divider /2/4/16/32 Freescale Semiconductor, Inc... Clock logic Select SPI control SPI status register 10 SPIF WCOL MODF SPIE SPE DOD MSTR CPOL CPHA SPR1 SPR0 SPI control register SPI interrupt request Internal data bus Figure 10-2 Serial peripheral interface block diagram TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com SERIAL PERIPHERAL INTERFACE MOTOROLA 10-5 Freescale Semiconductor, Inc. Master MISO 8-bit shift register MISO Slave 8-bit shift register MOSI MOSI Freescale Semiconductor, Inc... SCK SPI clock generator SS V DD SCK SS Figure 10-3 Serial peripheral interface master-slave interconnection 10 10.4 SPI registers There are three registers in the serial peripheral interface which provide control, status and data storage functions. These registers are called: the serial peripheral control register (SPCR), the serial peripheral status register (SPSR) and the serial peripheral data I/O register (SPDAT). 10.4.1 Control register (SPCR) Address bit 7 SPIE bit 6 SPE bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset SPI control register (SPCR) $0044 DOD MSTR CPOL CPHA SPR1 SPR0 0000 01uu SPIE -- SPI interrupt enable 1 (set) - SPI interrupts enabled. SPI interrupts disabled. 0 (clear) - When this bit is set to one, a hardware interrupt sequence is requested each time the SPIF or MODF status flag is set. SPI interrupts are inhibited if this bit is clear or if the I bit in the CC register is set. TPG MOTOROLA 10-6 For More Information On This Product, Go to: www.freescale.com SERIAL PERIPHERAL INTERFACE MC68HC05F32 Freescale Semiconductor, Inc. SPE -- SPI system enable 1 (set) - SPI system on. SPI system off. 0 (clear) - When the SPE bit is set, port C pins 4, 5, 6, and 7 are dedicated to the SPI function. DOD -- Direction of data This bit determines the direction of the data flow in or out of the serial shift register. 1 (set) - data is transferred LSB first. data is transferred MSB first (default state). Freescale Semiconductor, Inc... 0 (clear) - MSTR -- Master/slave mode select 1 (set) - master mode is selected. slave mode is selected. 0 (clear) - CPOL -- Clock polarity When the clock polarity bit is cleared and data is not being transferred, a steady state low value is produced at the SCK pin of the master device. Conversely, if this bit is set, the SCK pin will idle high. This bit is also used in conjunction with the clock phase control bit to produce the desired clock-data relationship between master and slave. See Figure 10-1. CPHA -- Clock phase The clock phase bit, in conjunction with the CPOL bit, controls the clock-data relationship between master and slave. The CPOL bit can be thought of simply as inserting an inverter in series with the SCK line. The CPHA bit selects one of two fundamentally different clocking protocols. When CPHA = 0, the shift clock is the logical OR of SCK and SS. As soon as SS goes low, the transaction begins and the first edge on SCK invokes the first data sample. When CPHA = 1, the SS pin may be thought of as a simple output enable control. Refer to Figure 10-1. SPR1, SPR0 -- SPI clock (SCK) rate select bits If the device is a master, the two serial peripheral rate bits select one of four division ratios of the E-clock to be used as SCK (See Table 10-1). These bits have no effect in slave mode. 10 TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com SERIAL PERIPHERAL INTERFACE MOTOROLA 10-7 Freescale Semiconductor, Inc. Table 10-1 SPI rate selection E clock divided by 2 4 16 32 SPR1 0 0 1 1 SPR0 0 1 0 1 Freescale Semiconductor, Inc... 10.4.2 Status register (SPSR) Address bit 7 bit 6 bit 5 0 bit 4 MODF bit 3 0 bit 2 0 bit 1 0 0 bit 0 State on reset 0000 0000 SPI status register (SPSR) $0045 SPIF WCOL SPIF -- SPI interrupt request flag The serial peripheral data transfer flag bit is set after the eighth SCK cycle in a data transfer and it is cleared by reading the SPSR register (with SPIF set) followed by reading from or writing to the SPI data register (SPDAT). WCOL -- Write collision The write collision bit is used to indicate that a serial transfer was in progress when the MCU tried to write new data into the SPDAT data register. The MCU write is disabled to avoid writing over the data being transmitted. No interrupt is generated because the error status flag can be read upon completion of the transfer that was in progress at the time of the error. This flag is automatically cleared by a read of the SPSR (with WCOL set) followed by an access (read or write) to the SPDAT register. MODF -- SPI mode error interrupt status flag This flag is set if the SS signal goes to its active-low level while the SPI is configured as a master (MSTR = 1). This condition is not permitted in normal operation. This flag is automatically cleared by a read of the SPSR (with MODF set) followed by a write to the SPCR register. 10 TPG MOTOROLA 10-8 For More Information On This Product, Go to: www.freescale.com SERIAL PERIPHERAL INTERFACE MC68HC05F32 Freescale Semiconductor, Inc. 10.4.3 SPI data I/O register (SPDAT) Address SPI data/IO register (SPDAT) $0046 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset uuuu uuuu Freescale Semiconductor, Inc... The serial peripheral data I/O register is used to transmit and receive data on the serial bus. Only a write to this register will initiate transmission/reception of another byte, and this will only occur in the master device. At the completion of transmitting a byte of data, the SPIF status bit is set in both the master and slave devices. When the user reads the serial peripheral data I/O register, a buffer is actually being read. The first SPIF must be cleared by the time a second transfer of data from the shift register to the read buffer is initiated or an overrun condition will exist. In cases of overrun, the byte which causes the overrun is lost. A write to the serial peripheral data I/O register is not buffered and places data directly into the shift register for transmission. 10.5 SPI during WAIT mode When the MCU enters wait mode, the CPU clock is halted. All CPU action is suspended; however, the SPI system remains active. In fact an interrupt from the SPI causes the processor to exit the wait mode. 10 10.6 SPI during STOP mode When the MCU enters the stop mode, the internal oscillator is turned off, and the baud rate generator which drives the SPI shuts down. This essentially stops all master mode SPI operation, thus transfer is halted until the MCU exits the stop mode. If the stop mode is exited by a reset, then the appropriate control/status bits are cleared and the SPI is disabled. If the device is in the slave mode when the stop instruction is executed, the slave SPI will still operate. It can still accept data and clock information in addition to transmitting its own data back to a master device. At the end of a possible transmission with a slave SPI in the stop mode, no flags are set until the MCU is "waked up" by an interrupt (IRQ, keyboard, LVI or CPI). Caution should be observed when operating the SPI (as a slave) during the stop mode because none of the protection circuitry (write collision, mode fault, etc.) is active. TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com SERIAL PERIPHERAL INTERFACE MOTOROLA 10-9 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... 10 THIS PAGE LEFT BLANK INTENTIONALLY TPG MOTOROLA 10-10 For More Information On This Product, Go to: www.freescale.com SERIAL PERIPHERAL INTERFACE MC68HC05F32 Freescale Semiconductor, Inc. 11 SERIAL COMMUNICATIONS INTERFACE A full-duplex asynchronous serial communications interface (SCI) is provided with a standard non-return-to-zero (NRZ) format and a variety of baud rates. The SCI transmitter and receiver are functionally independent and have their own baud rate generator; however they use the same baud rate and data format. The serial data format is standard mark/space (NRZ) and provides one start bit, eight or nine data bits, and one stop bit. Any SCI bidirectional communication requires a two-wire system: receive data in (RDI) and transmit data out (TDO). `Baud' and `bit rate' are used synonymously in the following description. Freescale Semiconductor, Inc... 11.1 * * * * * * * * SCI two-wire system features Standard NRZ (mark/space) format Advanced error detection method with noise detection for noise duration of up to 1/16th bit time Full-duplex operation (simultaneous transmit and receive) 32 software selectable baud rates Software selectable word length (eight or nine bits) Separate transmitter and receiver enable bits Interrupt drive capability Four separate enable bits for interrupt control 11 TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com SERIAL COMMUNICATIONS INTERFACE MOTOROLA 11-1 Freescale Semiconductor, Inc. Internal bus SCI interrupt + $0047 (See note) Transmit data register $0047 (See note) Receive data register Freescale Semiconductor, Inc... & TDO/ PC3 pin Transmit data shift register & & & + SCSR $004A 7 TRDE 6 TC 5 RDRF 4 IDLE OR 3 2 NF 1 FE $0049 SCCR2 TIE TCIE RIE ILIE TE RE SBK RWU 7 6 5 4 3 2 1 0 Receive data shift register RDI/ PC2 pin Wake up unit TE SBK 7 Flag control Receiver control Receiver clock Rate generator Transmitter control Transmitter clock 11 TCLR 0 SCP1 SCP0 RCKB SCR2 SCR1 SCR0 BAUD, $004B 7 R8 6 T8 5 M 4 3 WAKE 2 0 1 0 0 0 SCCR1 $0048 Note: The serial communications data register (SCDAT) is controlled by the internal R/W signal. It is the transmit data register when written to and the receive data register when read. Figure 11-1 Serial communications interface block diagram TPG MOTOROLA 11-2 For More Information On This Product, Go to: www.freescale.com SERIAL COMMUNICATIONS INTERFACE MC68HC05F32 Freescale Semiconductor, Inc. 11.2 * * * * * * SCI receiver features Receiver wake-up function (idle line or address bit) Idle line detection Framing error detection Noise detection Overrun detection Receiver data register full flag Freescale Semiconductor, Inc... 11.3 * * * SCI transmitter features Transmit data register empty flag Transmit complete flag Send break 11.4 External connections The external operation of the SCI block is routed through bits 2 and 3 of port C. Bits PC2 and PC3 are the receive and transmit pins for the SCI (RDI, TDO). Refer to Section 4 for a full description of port C. 11 SCI TCLR 0 SCP1 SCP0 RCKB TDO SCR2 SCR1 RDI SCR0 SCCR2, $0049 7 Port C 6 5 4 3 2 1 0 PC2/RDI PC3/TDO Figure 11-2 SCI and port C TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com SERIAL COMMUNICATIONS INTERFACE MOTOROLA 11-3 Freescale Semiconductor, Inc. 11.5 Functional description A block diagram of the SCI is shown in Figure 11-1. Option bits in serial control register1 (SCCR1) select the `wake-up' method (WAKE bit) and data word length (M bit) of the SCI. SCCR2 provides control bits that individually enable the transmitter and receiver, enable system interrupts and provide the wake-up enable bit (RWU) and the send break code bit (SBK). Control bits in the baud rate register (BAUD) allow the user to select one of 32 different baud rates for the transmitter and receiver (see Section 11.11.5). Data transmission is initiated by writing to the serial communications data register (SCDR). Provided the transmitter is enabled, data stored in the SCDR is transferred to the transmit data shift register. This transfer of data sets the transmit data register empty flag (TDRE) in the SCI status register (SCSR) and generates an interrupt (if transmitter interrupts are enabled). The transfer of data to the transmit data shift register is synchronized with the bit rate clock. All data is transmitted least significant bit first. Upon completion of data transmission, the transmission complete flag (TC) in the SCSR is set (provided no pending data, preamble or break is to be sent) and an interrupt is generated (if the transmit complete interrupt is enabled). If the transmitter is disabled, and the data, preamble or break (in the transmit data shift register) has been sent, the TC bit will also be set. This will also generate an interrupt if the transmission complete interrupt enable bit (TCIE) is set. If the transmitter is disabled during a transmission, the character being transmitted will be completed before the transmitter gives up control of the TDO pin. When SCDR is read, it contains the last data byte received, provided that the receiver is enabled. The receive data register full flag bit (RDRF) in the SCSR is set to indicate that a data byte has been transferred from the input serial shift register to the SCDR; this will cause an interrupt if the receiver interrupt is enabled. The data transfer from the input serial shift register to the SCDR is synchronized by the receiver bit rate clock. The OR (overrun), NF (noise), or FE (framing) error flags in the SCSR may be set if data reception errors occurred. An idle line interrupt is generated if the idle line interrupt is enabled and the IDLE bit (which detects idle line transmission) in SCSR is set. This allows a receiver that is not in the wake-up mode to detect the end of a message or the preamble of a new message, or to resynchronize with the transmitter. A valid character must be received before the idle line condition or the IDLE bit will not be set and idle line interrupt will not be generated. Freescale Semiconductor, Inc... 11 TPG MOTOROLA 11-4 For More Information On This Product, Go to: www.freescale.com SERIAL COMMUNICATIONS INTERFACE MC68HC05F32 Freescale Semiconductor, Inc. 11.6 Data format Receive data or transmit data is the serial data that is transferred to the internal data bus from the receive data input pin (RDI) or from the internal bus to the transmit data output pin (TDO). The non-return-to-zero (NRZ) data format shown in Figure 11-3 is used and must meet the following criteria: - - - - - The idle line is brought to a logic one state prior to transmission/reception of a character. A start bit (logic zero) is used to indicate the start of a frame. The data is transmitted and received least significant bit first. A stop bit (logic one) is used to indicate the end of a frame. A frame consists of a start bit, a character of eight or nine data bits, and a stop bit. A break is defined as the transmission or reception of a low (logic zero) for at least one complete frame time (10 zeros for 8-bit format, 11 zeros for 9-bit). Control bit M selects 8 or 9 bit data Freescale Semiconductor, Inc... 0 Idle line 0 1 2 3 4 5 6 7 8 Start Stop Start Figure 11-3 Data format 11 11.7 Receiver wake-up operation The receiver logic hardware also supports a receiver wake-up function which is intended for systems having more than one receiver. With this function a transmitting device directs messages to an individual receiver or group of receivers by passing addressing information as the initial byte(s) of each message. The wake-up function allows receivers not addressed to remain in a dormant state for the remainder of the unwanted message. This eliminates any further software overhead to service the remaining characters of the unwanted message and thus improves system performance. The receiver is placed in wake-up mode by setting the receiver wake-up bit (RWU) in the SCCR2 register. While RWU is set, all of the receiver related status flags (RDRF, IDLE, OR, NF, and FE) are inhibited (cannot become set). Note that the idle line detect function is inhibited while the RWU bit is set. Although RWU may be cleared by a software write to SCCR2, it would be unusual to do so. Normally RWU is set by software and is cleared automatically in hardware by one of the two methods described below. TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com SERIAL COMMUNICATIONS INTERFACE MOTOROLA 11-5 Freescale Semiconductor, Inc. 11.7.1 Idle line wake-up In idle line wake-up mode, a dormant receiver wakes up as soon as the RDI line becomes idle. Idle is defined as a continuous logic high level on the RDI line for ten (or eleven) full bit times. Systems using this type of wake-up must provide at least one character time of idle between messages to wake up sleeping receivers, but must not allow any idle time between characters within a message. Freescale Semiconductor, Inc... 11.7.2 Address mark wake-up In address mark wake-up, the most significant bit (MSB) in a character is used to indicate whether it is an address (1) or data (0) character. Sleeping receivers will wake up whenever an address character is received. Systems using this method for wake-up would set the MSB of the first character of each message and leave it clear for all other characters in the message. Idle periods may be present within messages and no idle time is required between messages for this wake-up method. 11.8 Receive data in (RDI) 11 Receive data is the serial data that is applied through the input line and the SCI to the internal bus. The receiver circuitry clocks the input at a rate equal to 16 times the baud rate. This time is referred to as the RT rate in Figure 11-5. The receiver clock generator is controlled by the baud rate register, as shown in Figure 11-1; however, the SCI is synchronized by the start bit, independent of the transmitter. Once a valid start bit is detected, the start bit, each data bit and the stop bit are sampled three times at RT intervals 8 RT, 9 RT and 10 RT (1 RT is the position where the bit is expected to start), as shown in Figure 11-4. The value of the bit is determined by voting logic which takes the value of the majority of the samples. A noise flag is set when all three samples on a valid start bit or data bit or the stop bit do not agree . Previous bit RDI 16RT 1RT Present bit Samples Next bit 8RT 9RT 10RT < < < 16RT 1RT Figure 11-4 SCI sampling technique used on all bits TPG MOTOROLA 11-6 For More Information On This Product, Go to: www.freescale.com SERIAL COMMUNICATIONS INTERFACE MC68HC05F32 Freescale Semiconductor, Inc. 16X internal sampling clock RT clock edges for all three examples Idle RDI 1 1 1 1 1 1 1 1 1 1 1 Start qualifiers 1RT 2RT 3RT 4RT 5RT 6RT 7RT 8RT Start 0 0 0 0 Start edge verification samples Noise Freescale Semiconductor, Inc... Start RDI 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 Noise RDI 1 1 1 1 1 0 1 1 1 1 1 Start 0 0 0 0 Figure 11-5 SCI examples of start bit sampling technique 11.9 Start bit detection When the input (idle) line is detected low, it is tested for three more sample times (referred to as the start edge verification samples in Figure 11-5). If at least two of these three verification samples detect a logic zero, a valid start bit has been detected, otherwise the line is assumed to be idle. A noise flag is set if one of the three verification samples detect a logic one, thus a valid start bit could be assumed with a set noise flag present. If there has been a framing error without detection of a break (10 zeros for 8 bit format or 11 zeros for 9 bit format), the circuit continues to operate as if there actually was a stop bit, and the start edge will be placed artificially. The last bit received in the data shift register is inverted to a logic one, and the three logic one start qualifiers (shown in Figure 11-5) are forced into the sample shift register during the interval when detection of a start bit is anticipated (see Figure 11-6); therefore, the start bit will be accepted no sooner than it is anticipated. If the receiver detects that a break (RDRF = 1, FE = 1, receiver data register = $00) produced the framing error, the start bit will not be artificially induced and the receiver must actually detect a logic one before the start bit can be recognised (see Figure 11-7). 11 TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com SERIAL COMMUNICATIONS INTERFACE MOTOROLA 11-7 Freescale Semiconductor, Inc. Data Expected stop Artificial edge Data RDI Start bit Data samples a) Case 1: receive line low during artificial edge Freescale Semiconductor, Inc... Data Expected stop Start edge Data RDI Start bit Data samples b) Case 2: receive line high during expected start edge Figure 11-6 Artificial start following a framing error Expected stop Break RDI Detected as valid start edge Start bit 11 Data samples Start qualifiers Start edge verification samples Figure 11-7 SCI start bit following a break 11.10 Transmit data out (TDO) Transmit data is the serial data from the internal data bus that is applied through the SCI to the output line. Data format is as discussed in Section 11.6 and shown in Figure 11-3. The transmitter generates a bit time by using a derivative of the RT clock, thus producing a transmission rate equal to 1/16th that of the receiver sample clock. TPG MOTOROLA 11-8 For More Information On This Product, Go to: www.freescale.com SERIAL COMMUNICATIONS INTERFACE MC68HC05F32 Freescale Semiconductor, Inc. 11.11 SCI registers The SCI system is configured and controlled by five registers: SCDAT, SCCR1, SCCR2, SCSR, and BAUD. 11.11.1 Serial communications data register (SCDAT) Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset undefined Freescale Semiconductor, Inc... SCI data (SCDAT) $0047 The SCDAT is controlled by the internal R/W signal and performs two functions in the SCI. It acts as the receive data register (RDR) when it is read and as the transmit data register (TDR) when it is written. Figure 11-1 shows this register as two separate registers, RDR and TDR. The RDR provides the interface from the receive shift register to the internal data bus and the TDR provides the parallel interface from the internal data bus to the transmit shift register. The receive data register is a read-only register containing the last byte of data received from the shift register for the internal data bus. The RDR full bit (RDRF) in the serial communications status register is set to indicate that a byte has been transferred from the input serial shift register to the SCDAT. The transfer is synchronized with the receiver bit rate clock (from the receiver control) as shown in Figure 11-1. All data is received with the least significant bit first. The transmit data register (TDR) is a write-only register containing the next byte of data to be applied to the transmit shift register from the internal data bus. As long as the transmitter is enabled, data stored in the SCDAT is transferred to the transmit shift register (after the current byte in the shift register has been transmitted). The transfer is synchronized with the transmitter bit rate clock (from the transmitter control) as shown in Figure 11-1. All data is received with the least significant bit first. 11 11.11.2 Serial communications control register 1 (SCCR1) Address bit 7 R8 bit 6 T8 bit 5 0 bit 4 M bit 3 WAKE bit 2 0 bit 1 0 0 bit 0 State on reset 0000 0000 SCI control 1 (SCCR1) $0048 The SCI control register 1 (SCCR1) contains control bits related to the nine data bit character format and the receiver wake-up feature. TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com SERIAL COMMUNICATIONS INTERFACE MOTOROLA 11-9 Freescale Semiconductor, Inc. R8 -- Receive data bit 8 This read-only bit is the ninth serial data bit received when the SCI system is configured for nine data bit operation (M = 1). The most significant bit (bit 8) of the received character is transferred into this bit at the same time as the remaining eight bits (bits 7-0) are transferred from the serial receive shift register to the SCI receive data register. T8 -- Transmit data bit 8 This read/write bit is the ninth data bit to be transmitted when the SCI system is configured for nine data bit operation (M = 1). When the eight low order bits (bits 7-0) of a transmit character are transferred from the SCI data register to the serial transmit shift register, this bit (bit 8) is transferred to the ninth bit position of the shift register. M -- Mode (select character format) The read/write M-bit controls the character length for both the transmitter and receiver at the same time. The 9th data bit is most commonly used as an extra stop bit or it can also be used as a parity bit (see Table 11-1). 1 (set) - Start bit, 9 data bits, 1 stop bit. Start bit, 8 data bits, 1 stop bit. Freescale Semiconductor, Inc... 0 (clear) - Table 11-1 Method of receiver wake-up WAKE 0 1 1 x = Don't care M x 0 1 Method of receiver wake-up Detection of an idle line allows the next data type received to cause the receive data register to fill and produce an RDRF flag. Detection of a received one in the eighth data bit allows an RDRF flag and associated error flags. Detection of a received one in the ninth data bit allows an RDRF flag and associated error flags. 11 WAKE -- Wake-up mode select This bit allows the user to select the method for receiver wake-up. The WAKE bit can be read or written to any time. See Table 11-1. 1 (set) - Wake-up on address mark; if RWU is set, SCI will wake-up if the 8th (if M = 0) or the 9th (if M = 1) bit received on the Rx line is set. Wake-up on idle line; if RWU is set, SCI will wake-up after 11 (if M = 0) or 12 (if M = 1) consecutive `1's on the Rx line. 0 (clear) - TPG MOTOROLA 11-10 For More Information On This Product, Go to: www.freescale.com SERIAL COMMUNICATIONS INTERFACE MC68HC05F32 Freescale Semiconductor, Inc. 11.11.3 Serial communications control register 2 (SCCR2) The SCI control register 2 (SCCR2) provides the control bits that enable/disable individual SCI functions. Address SCI control (SCCR2) $0049 bit 7 TIE bit 6 TCIE bit 5 RIE bit 4 ILIE bit 3 TE bit 2 RE bit 1 RWU bit 0 SBK State on reset 0000 0000 Freescale Semiconductor, Inc... TIE -- Transmit interrupt enable 1 (set) - TDRE interrupts enabled. TDRE interrupts disabled. 0 (clear) - TCIE -- Transmit complete interrupt enable 1 (set) - TC interrupts enabled. TC interrupts disabled. 0 (clear) - RIE -- Receiver interrupt enable 1 (set) - RDRF and OR interrupts enabled. RDRF and OR interrupts disabled. 0 (clear) - ILIE -- Idle line interrupt enable 1 (set) - IDLE interrupts enabled. IDLE interrupts disabled. 11 0 (clear) - TE -- Transmitter enable When the transmit enable bit is set, the transmit shift register output is applied to the TDO line. Depending on the state of control bit M (SCCR1), a preamble of 10 (M = 0) or 11 (M = 1) consecutive ones is transmitted when software sets the TE bit from a cleared state. After loading the last byte in the serial communications data register and receiving the TDRE flag, the user should clear TE. Transmission of the last byte will then be completed before the transmitter gives up control of the TDO pin. While the transmitter is active, PC3 is forced to be an output. 1 (set) - Transmitter enabled. Transmitter disabled. 0 (clear) - TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com SERIAL COMMUNICATIONS INTERFACE MOTOROLA 11-11 Freescale Semiconductor, Inc. RE -- Receiver enable 1 (set) - Receiver enabled. Receiver disabled. 0 (clear) - When RE is clear (receiver disabled) all the status bits associated with the receiver (RDRF, IDLE, OR, NF and FE) are inhibited. While the receiver is enabled, PC2 is forced to be an input. RWU -- Receiver wake-up When the receiver wake-up bit is set by the user software, it puts the receiver to sleep and enables the wake-up function. The type of wake-up mode for the receiver is determined by the WAKE bit discussed above (in SCCR1). When the RWU bit is set, no status flags will be set. Flags which were set previously will not be cleared when RWU is set. If the WAKE bit is cleared, RWU is cleared by the SCI logic after receiving 10 (M = 0) or 11 (M =1) consecutive ones. Under these conditions, RWU cannot be set if the line is idle. If the WAKE bit is set, RWU is cleared after receiving an address bit. The RDRF flag will then be set and the address byte stored in the receiver data register. SBK -- Send break If the send break bit is toggled set and cleared, the transmitter sends 10 (M = 0) or 11 (M = 1) zeros and then reverts to idle sending data. If SBK remains set, the transmitter will continually send whole blocks of zeros (sets of 10 or 11) until cleared. At the completion of the break code, the transmitter sends at least one high bit to guarantee recognition of a valid start bit. If the transmitter is currently empty and idle, setting and clearing SBK is likely to queue two character times of break because the first break transfers almost immediately to the shift register and the second is then queued into the parallel transmit buffer. Freescale Semiconductor, Inc... 11 11.11.4 Serial communications status register (SCSR) Address bit 7 TDRE bit 6 TC bit 5 RDRF bit 4 IDLE bit 3 OR bit 2 NF bit 1 FE 0 bit 0 State on reset SCI status (SCSR) $004A 1100 0000 The serial communications status register (SCSR) provides inputs to the interrupt logic circuits for generation of the SCI system interrupt. In addition, a noise flag bit and a framing error bit are also contained in the SCSR. TPG MOTOROLA 11-12 For More Information On This Product, Go to: www.freescale.com SERIAL COMMUNICATIONS INTERFACE MC68HC05F32 Freescale Semiconductor, Inc. TDRE -- Transmit data register empty flag This bit is set when the contents of the transmit data register are transferred to the serial shift register. New data will not be transmitted unless the SCSR register is read before writing to the transmit data register to clear the TDRE flag. If the TDRE bit is clear, this indicates that the transfer has not yet occurred and a write to the serial communications data register will overwrite the previous value. The TDRE bit is cleared by accessing the serial communications status register (with TDRE set) followed by writing to the serial communications data register. TC -- Transmit complete flag This bit is set to indicate that the SCI transmitter has no meaningful information to transmit (no data in shift register, no preamble, no break). When TC is set the serial line will go idle (continuous MARK). The TC bit is cleared by accessing the serial communications data register (with TC set) followed by writing to the serial communications data register. It does not inhibit the transmitter function in any way. RDRF -- Receive data register full flag This bit is set when the contents of the receiver serial shift register are transferred to the receiver data register. If multiple errors are detected in any one received word, the NF and RDRF bits will be affected as appropriate during the same clock cycle. The RDRF bit is cleared when the serial communications status register is accessed (with RDRF set) followed by a read of the serial communications data register. IDLE -- Idle line detected flag This bit is set when a receiver idle line is detected (the receipt of a minimum of ten/eleven consecutive `1's). This bit will not be set by the idle line condition when the RWU bit is set. This allows a receiver that is not in the wake-up mode to detect the end of a message, detect the preamble of a new message or resynchronize with the transmitter. The IDLE bit is cleared by accessing the serial communications status register (with IDLE set) followed by a read of the serial communications data register. Once cleared, IDLE will not be set again until after RDRF has been set, (i.e. until after the line has been active and becomes idle again). OR -- Overrun error flag This bit is set when a new byte is ready to be transferred from the receiver shift register to the receiver data register and the receive data register is already full (RDRF bit is set). Data transfer is inhibited until the RDRF bit is cleared. Data in the serial communications data register is valid in this case, but additional data received during an overrun condition (including the byte causing the overrun) will be lost. The OR bit is cleared when the serial communications status register is accessed (with OR set) followed by a read of the serial communications data register. Freescale Semiconductor, Inc... 11 TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com SERIAL COMMUNICATIONS INTERFACE MOTOROLA 11-13 Freescale Semiconductor, Inc. NF -- Noise error flag This bit is set if there is noise on a `valid' start bit, any of the data bits or on the stop bit. The NF bit is not set by noise on the idle line nor by invalid start bits. If there is noise, the NF bit is not set until the RDRF flag is set. Each data bit is sampled three times as described in Section 11.8. The NF bit represents the status of the byte in the serial communications data register. For the byte being received (shifted in) there will be also a `working' noise flag, the value of which will be transferred to the NF bit when the serial data is loaded into the serial communications data register. The NF bit does not generate an interrupt because the RDRF bit gets set with NF and can be used to generate the interrupt. The NF bit is cleared when the serial communications status register is accessed (with NF set) followed by a read of the serial communications data register. FE -- Framing error flag This bit is set when the word boundaries in the bit stream are not synchronized with the receiver bit counter (generated by the reception of a logic zero bit where a stop bit was expected). The FE bit reflects the status of the byte in the receive data register and the transfer from the receive shift register to the receive data register is inhibited by an overrun. The FE bit is set during the same cycle as the RDRF bit but does not get set in the case of an overrun (OR). The framing error flag inhibits further transfer of data into the receive data register until it is cleared. The FE bit is cleared when the serial communications status register is accessed (with FE set) followed by a read of the serial communications data register. Freescale Semiconductor, Inc... 11 11.11.5 Baud rate register (BAUD) The baud rate register (BAUD) is used to set the bit rate for the SCI system. Normally this register is written once, during initialization, to set the baud rate for SCI communications. Both the receiver and the transmitter use the same baud rate which is derived from the MCU bus rate clock. A two stage divider is used to develop custom baud rates from normal MCU crystal frequencies, therefore it is not necessary to use special baud rate crystal frequencies. Address SCI baud rate (BAUD) $004B bit 7 TCLR bit 6 0 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset SCP1 SCP0 RCKB SCR2 SCR1 SCR0 0000 0uuu TCLR -- Clear baud rate counters (test purposes only) This bit is disabled and remains low in any mode other than test or bootstrap. Reset clears this bit. While in test or bootstrap mode, setting this bit causes the baud rate counter chains to be reset. The logic one state of this bit is transitory, reads always a return a logic zero. This control bit is only intended for factory testing of the MCU TPG MOTOROLA 11-14 For More Information On This Product, Go to: www.freescale.com SERIAL COMMUNICATIONS INTERFACE MC68HC05F32 Freescale Semiconductor, Inc. SCP1, SCP0 -- Serial prescaler select bits These read/write bits determine the prescale factor by which the internal processor clock is divided before it is applied to the transmitter and receiver rate control dividers. This common prescaled output is used as the input to a divider that is controlled by the SCR0-SCR2 bits for the SCI receiver and transmitter. Table 11-2 First prescaler stage Prescaler division ratio (PRS1) 1 3 4 13 Freescale Semiconductor, Inc... SCP1 0 0 1 1 SCP0 0 1 0 1 SCR2, SCR1, SCR0 -- SCI rate select bits These three read/write bits select the baud rates for the transmitter and the receiver. The prescaler output is divided by the factors shown in Table 11-3. Table 11-3 Second prescaler stage Prescaler division ratio (PRS2) 1 2 4 8 16 32 64 128 SCR2 0 0 0 0 1 1 1 1 SCR1 0 0 1 1 0 0 1 1 SCR0 0 1 0 1 0 1 0 1 11 RCKB -- SCI receive baud rate clock test This bit is disabled and remains low in any mode other than test or bootstrap. Reset clears this bit. While in test or bootstrap mode, this bit may be written but not read (reads always return a logic zero). Setting this bit enables a baud rate counter test mode, where the exclusive-or of the receiver clock (16 times the baud rate) is driven out of the PC3/TDO pin. This control bit is intended only for factory testing of the MCU. TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com SERIAL COMMUNICATIONS INTERFACE MOTOROLA 11-15 Freescale Semiconductor, Inc. 11.12 Baud rate selection The flexibility of the baud rate generator allows many different baud rates to be selected, depending on the CPU clock frequency. A particular baud rate may be generated by manipulating the various prescaler and division ratio bits. The SCI baud rate can be calculated from the internal bus clock and the two prescaler factors, PRS1 and PRS2. The first prescaler factor, PRS1, is selected with SCP0 and SCP1, as shown in Table 11-2. The second prescaler factor, PRS2, is selected with SCR0, SCR1 and SCR2, as shown in Table 11-3. The SCI baud rate B equals the internal bus clock E, divided by 16, divided by PRS1, divided by PRS2 (B = E/16/PRS1/PRS2). Freescale Semiconductor, Inc... Note: For the receiver, the internal clock frequency is 16 times higher than the selected baud rate. 11.13 SCI during STOP mode When the MCU enters STOP mode, the baud rate generator driving the receiver and transmitter is shut down. This stops all SCI activity. Both the receiver and the transmitter are unable to operate. If the STOP instruction is executed during a transmitter transfer, that transfer is halted. When STOP mode is exited as a result of an external interrupt, that particular transmission resumes. If the receiver is receiving data when the STOP instruction is executed, received data sampling is stopped (baud generator stops) and the rest of the data is lost. Warning: For the above reasons, all SCI transactions should be in the idle state when the STOP instruction is executed. 11 11.14 SCI during WAIT mode The SCI system is not affected by WAIT mode and continues normal operation. Any valid SCI interrupt will wake-up the system. If required, the SCI system can be disabled prior to entering WAIT mode by writing a zero to the transmitter and receiver enable bits in the serial communication control register 2 at $0049. This action will result in a reduction of power consumption during WAIT mode. TPG MOTOROLA 11-16 For More Information On This Product, Go to: www.freescale.com SERIAL COMMUNICATIONS INTERFACE MC68HC05F32 Freescale Semiconductor, Inc. 12 PULSE WIDTH MODULATOR 12.1 PWM introduction Freescale Semiconductor, Inc... The pulse width modulator (PWM) system has three 8-bit channels (PWM1, PWM2, and PWM3). The PWM has a programmable period of 256xT, where T can be E/2, E/4, and E/8 for an output frequency of 4 KHz, 2KHz, and 1 KHz respectively with E = 2MHz. E is the internal bus frequency fixed to half of the external oscillator frequency. PWM control register ($0040) 0 0 0 POL3 POL2 POL1 RA1 RA0 PWM3 data ($0043) PWM3/PE7 PWM 8-bit counter PWM2 data ($0042) PWM2/PE6 12 PWM1 data ($0041) PWM1PE5 Clock E Figure 12-1 PWM block diagram TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com PULSE WIDTH MODULATOR MOTOROLA 12-1 Freescale Semiconductor, Inc. 12.2 Functional description The PWM is capable of generating signals from 0% to 100% duty cycle. A $00 in the PWM data register yields an `OFF' output (0%), but an $FF yields a duty of 255/256. To achieve the 100% duty (`ON' output), the polarity control bit is set to active low (POL = 0) for that channel (i.e. PWM0 and PWM1) while the data register has $00 in it. When not in use, the PWM system can be shut off to save power by clearing the clock rate select bits RA0 and RA1 in the PWM control register (PWCR). The PWM starts conversion immediately after programming bits RA0 and RA1 in the PWM control register. The PWM outputs are connected to port E if the corresponding bit in the port E control register is set. The PWM output can have an active high or an active low pulse under software control. Freescale Semiconductor, Inc... $00 256 T $01 T 255 T $50 176 T $80 128 T 12 $FF 255 T T Figure 12-2 PWM output waveforms (POL = 1, active high) 12.3 Registers There are three PWM data registers and a control register associated with the PWM system. These registers can be written to and read at any time. After reset the user should write to the data registers and to the polarity select bits prior to enabling the PWM system (i.e. prior to setting RA1 and/or RA0 for PWM input clock rate). This will avoid an erroneous duty cycle being driven. TPG MOTOROLA 12-2 For More Information On This Product, Go to: www.freescale.com PULSE WIDTH MODULATOR MC68HC05F32 Freescale Semiconductor, Inc. $00 256 T $01 T 255 T Freescale Semiconductor, Inc... $50 80 T $80 128 T $FF 255 T T Figure 12-3 PWM waveforms (POL = 0, active low) 12.3.1 PWM control (PWMCR) Address bit 7 0 bit 6 0 bit 5 0 bit 4 bit 3 bit 2 bit 1 RA1 bit 0 RA0 State on reset PWM control (PWMCR) $0040 POL3 POL2 POL1 0001 1100 POL1 -- PWM1 polarity 1 (set) - makes the PWM1 pulse active high makes the PWM1 pulse active low 12 0 (clear) - POL2 -- PWM2 polarity 1 (set) - makes the PWM2 pulse active high makes the PWM2 pulse active low 0 (clear) - POL3 -- PWM3 polarity 1 (set) - makes the PWM3 pulse active high makes the PWM3 pulse active low 0 (clear) - TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com PULSE WIDTH MODULATOR MOTOROLA 12-3 Freescale Semiconductor, Inc. RA1, RA0 -- PWM clock rate bits These bits select the input clock rate and determine the period. Note: The polarity bits and the PWM clock rate bits are not latched until the end of conversion. They affect the PWM output immediately. For proper operation these control bits must not be changed during conversion. Freescale Semiconductor, Inc... Table 12-1 PWM clock rate RA1:RA0 00 01 10 11 PWM input clock OFF E/2 E/4 E/8 12.3.2 PWM data registers (PWMD) The PWM system has three 8-bit data registers which hold the duty cycle for each PWM output. PWM data1, PWM data2, and PWM data3 are the data registers located at $41-$43 respectively. Note: These registers are affected by RESET 12 Address PWM data1 (PWMD1) PWM data2 (PWMD2) PWM data3 (PWMD3) $0041 $0042 $0043 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset 1000 0000 1000 0000 1000 0000 12.4 PWM during WAIT mode The PWM continues normal operation during WAIT mode. To decrease power consumption during WAIT, it is recommended that the rate select bits in the PWM control register are cleared if the PWM D/A converter is not used. TPG MOTOROLA 12-4 For More Information On This Product, Go to: www.freescale.com PULSE WIDTH MODULATOR MC68HC05F32 Freescale Semiconductor, Inc. 12.5 PWM during STOP mode In STOP mode the oscillator is stopped causing the PWM to cease operation. Any signal in process is aborted in whatever phase the signal happens to be in. 12.6 PWM during reset Freescale Semiconductor, Inc... Upon RESET the RA0 and RA1 bits in the PWM control register are cleared, the port E control register is cleared, the data registers are written with $80 and the polarity bits are set. This in effect disables the PWM system. The user should write to the data registers prior to enabling the PWM system (i.e. prior to setting RA1 or RA0). This will avoid an erroneous duty cycle being driven. 12 TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com PULSE WIDTH MODULATOR MOTOROLA 12-5 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... THIS PAGE LEFT BLANK INTENTIONALLY 12 TPG MOTOROLA 12-6 For More Information On This Product, Go to: www.freescale.com PULSE WIDTH MODULATOR MC68HC05F32 Freescale Semiconductor, Inc. 13 32 KHZ CLOCK SYSTEM 13.1 32 kHz clock system Freescale Semiconductor, Inc... The 32 kHz clock system is mostly independent from the rest of the MCU. WAIT mode and STOP mode do not affect the work of the 32 kHz clock system. For the reason of power saving the oscillator and the divider can be stopped if the oscillator input pin OSC3 is held on fixed potential. The 32 kHz clock system is provided to generate a refresh signal at port E pin 4 and an custom periodic interrupt (CPI) with a period of 0.5s. The refresh frequency and the periodic interrupt are under the control of the custom periodic interrupt control/status register located at $4C. 13.1.1 Custom periodic interrupt control/status register (CPICSR) The CPICSR contains the interrupt flag CPIF, the interrupt enable bit CPIE and refresh frequency select bits RFQ1, RFQ0. Address CPI control/status (CPICSR) $004C bit 7 0 bit 6 CPIF bit 5 0 bit 4 CPIE bit 3 0 bit 2 0 bit 1 bit 0 State on reset RFQ1 RFQ0 0000 0000 13 CPIF -- Custom periodic interrupt flag CPIF is a clearable, read-only status bit and is set when the 14-bit counter changes from $3FFF to $0000. A CPU interrupt request will be generated if CPIE is set. Clearing the CPIF is done by writing a `0' to it. Writing a `1' to CPIF has no effect on the bit's value. Reset clears CPIF. CPIE -- Custom periodic interrupt enable When this bit is cleared, the CPI interrupts are disabled. When this bit is set, a CPU interrupt request is generated when the CPIF bit is set. Reset clears this bit. TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com 32 KHZ CLOCK SYSTEM MOTOROLA 13-1 Freescale Semiconductor, Inc. RFQ1-RFQ0 -- Refresh frequency select These two read/write bits select one of four taps from the 14-stage counter to provide a refresh clock with a frequency according to Table 13-1. Reset clears these bits, selecting the highest frequency. Table 13-1 Refresh clock (32.768 kHz crystal) RFQ1 0 0 1 1 RFQ0 0 1 0 1 Refresh clock frequency 8.192 kHz (reset condition) 4.096 kHz 2.048 kHz 1.024 kHz Freescale Semiconductor, Inc... 13.1.1.1 Refresh clock If bit 4 in the control register of port E is set, the output of the 32 kHz clock system is connected to the pin PE4/REFRESH. The refresh clock rate is under software control and is specified in Table 13-1. 13.2 Operation during STOP mode Stop mode does not affect the work of the 32 kHz clock system. If the CPI interrupt is enabled, a custom periodic interrupt will cause the processor to wake up from the STOP mode. 13 13.3 Operation during WAIT mode The CPU clock halts during the WAIT mode, but the 32 kHz clock system remains active. If the CPI interrupt is enabled, a custom periodic interrupt will cause the processor to exit the WAIT mode. TPG MOTOROLA 13-2 For More Information On This Product, Go to: www.freescale.com 32 KHZ CLOCK SYSTEM MC68HC05F32 Freescale Semiconductor, Inc. 14 RESETS AND INTERRUPTS 14.1 Resets Freescale Semiconductor, Inc... The MC68HC05F32 can be reset in five ways: by the initial power-on reset function, by an active low input to the RESET pin, by an on-chip low voltage reset, by an opcode fetch from an illegal address, and by a COP watchdog timer reset. Any of these resets will cause the program to return to its starting address, specified by the contents of memory locations $FFFE and $FFFF, and cause the interrupt mask of the CCR to be set. 14.1.1 Power-on reset A power-on reset occurs when a positive transition is detected on VDD. The power-on reset function is strictly for power turn-on conditions and should not be used to detect drops in the power supply voltage. The power-on circuitry provides a stabilization delay (tPORL) from when the oscillator becomes active. If the external RESET pin is low at the end of this delay then the processor remains in the reset state until RESET goes high. 14.1.2 RESET pin When the oscillator is running in a stable state, the MCU is reset when a logic zero is applied to the RESET input for a minimum period of 1.5 machine cycles (tCYC). This pin contains an internal Schmitt trigger as part of its input to improve noise immunity. When the reset pin goes high, the MCU will resume operation on the following cycle. The RESET pin is also an output device for the internal low voltage reset. 14 14.1.3 Illegal address reset When an opcode fetch occurs from an address which is not part of the RAM ($0068 - $03FF) or of the ROM ($8000 - $FFFF) or EEPROM ($0400 - $04FF), the device is automatically reset. TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com RESETS AND INTERRUPTS MOTOROLA 14-1 Freescale Semiconductor, Inc. Note: No RTS or RTI instruction should be placed at the end of a memory block since this could result in an illegal address reset. 14.1.4 Computer operating properly (COP) reset The MCU contains a watchdog timer that automatically times out if not reset (cleared) within a specific time by a program reset sequence. If the COP watchdog timer is allowed to timeout, an internal reset is generated to reset the MCU. Because the internal reset signal is used, the MCU comes out of a COP reset in the same operating mode it was in when the COP timeout was generated. The COP function is a mask option, enabled or disabled during device manufacture. See Section 1.2. Refer to Section 5.3 for more information on the COP watchdog timer. Freescale Semiconductor, Inc... 14.1.5 Low voltage reset The MCU contains a low voltage detection circuit which drives the external reset. For a positive transition of supply voltage vDD, the low voltage reset occurs as long as VDD is below the VRON level. In this case the external reset pin is pulled down. If the supply voltage drops off above the VRON level, the reset is released. If the supply voltage falls off below the VROFF level, the RESET pin is pulled down. 14 TPG MOTOROLA 14-2 For More Information On This Product, Go to: www.freescale.com RESETS AND INTERRUPTS MC68HC05F32 Freescale Semiconductor, Inc. 14.2 Interrupts The MCU can be interrupted by nine different sources, eight maskable hardware interrupts and one nonmaskable software interrupt: * * * * * * * * * External signal on the IRQ pin; IRQ is mask selectable as edge or edge-and-level sensitive Keyboard interrupt Core timer interrupt 16-bit programmable timer interrupt Low voltage interrupt (LVI) - EEPROM Serial peripheral interface (SPI) interrupt Serial communications interface (SCI) interrupt 32 kHz clock system interrupt Software interrupt instruction (SWI) Freescale Semiconductor, Inc... Interrupts cause the processor to save the register contents on the stack and to set the interrupt mask (I-bit) to prevent additional interrupts. The RTI instruction (return from interrupt) causes the register contents to be recovered from the stack and normal processing to resume. While executing the RTI instruction, the interrupt mask bit (I-bit) will be cleared providing the corresponding enable bit stored on the stack is zero, i.e. the interrupt is disabled. Unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is complete. The current instruction is the one already fetched and being operated on. When the current instruction is complete, the processor checks all pending hardware interrupts. If interrupts are not masked (CCR I-bit clear) and the corresponding interrupt enable bit is set, the processor proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. Figure 14-1 shows the interrupt processing flow. Note: Power-on or external reset clears all interrupt enable bits thus preventing interrupts during the reset sequence. 14 TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com RESETS AND INTERRUPTS MOTOROLA 14-3 Freescale Semiconductor, Inc. 14.2.1 Interrupt priorities Each potential interrupt source is assigned a priority which means that if more than one interrupt is pending at the same time, the processor will service the one with the highest priority first. For example, if both an external interrupt and a timer interrupt are pending after an instruction execution, the external interrupt is serviced first. Freescale Semiconductor, Inc... 14.2.2 Non-maskable software interrupt (SWI) The software interrupt (SWI) is an executable instruction and a nonmaskable interrupt: it is executed regardless of the state of the I-bit in the CCR. If the I-bit is zero (interrupts enabled), SWI is executed after interrupts that were pending when the SWI was fetched, but before interrupts generated after the SWI was fetched. The SWI interrupt service routine address is specified by the contents of memory locations $FFFC and $FFFD. 14.2.3 Maskable hardware interrupts If the interrupt mask bit (I-bit) of the CCR is set, all maskable interrupts (internal and external) are masked. Clearing the I-bit allows interrupt processing to occur. IRQ is software selectable as either edge or edge-and-level sensitive (bit 3 of the system option register). Note: The internal interrupt latch is cleared in the first part of the interrupt service routine; therefore, one external interrupt pulse could be latched and serviced as soon as the I-bit is cleared. 14.2.3.1 Real time and core timer (CTIMER) interrupts 14 There are two different core timer interrupt flags that cause a CTIMER interrupt whenever an interrupt is enabled and its flag becomes set, namely RTIF and CTOF. The interrupt flags and enable bits are located in the CTIMER control and status register (CTCSR). These interrupts will vector to the same interrupt service routine, whose start address is contained in memory locations $FFF8 and $FFF9 (see Section 5.2.1 and Figure 5-1). To make use of the real time interrupt the RTIE bit must first be set. The RTIF bit will then be set after the specified number of counts. To make use of the core timer overflow interrupt, the CTOFE bit must first be set. The CTOF bit will then be set when the core timer counter register overflows from $FF to $00. TPG MOTOROLA 14-4 For More Information On This Product, Go to: www.freescale.com RESETS AND INTERRUPTS MC68HC05F32 Freescale Semiconductor, Inc. From RESET Is I-bit set ? No IRQ/Key external interrupt ? No Core timer or CPI interrupt ? No Timer1, 2, 3, 4 interrupt ? No LVI interrupt ? No SPI interrupt ? Yes Freescale Semiconductor, Inc... Yes Clear relevant interrupt request latch Yes Stack: PC, X, A, CC Yes Set I-bit Load PC from: SWI: IRQ/Key: CTIMER: CPI: TIMER: LVI: SPI: SCI: Yes $FFFC, $FFFD $FFFA, $FFFB $FFF8, $FFF9 $FFF8, $FFF9 $FFF6, $FFF7 $FFF4, $FFF5 $FFF2, $FFF3 $FFF0, $FFF1 Yes Fetch next instruction No SCI interrupt ? Yes SWI instruction ? No Yes RTI instruction ? No 14 Execute instruction No Restore registers from stack: CC, A, X, PC Figure 14-1 Interrupt flowchart TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com RESETS AND INTERRUPTS MOTOROLA 14-5 Freescale Semiconductor, Inc. Table 14-1 Vector address for interrupts and reset CPU Vector address interrupt RESET $FFFE-$FFFF SWI $FFFC-$FFFD IRQ $FFFA-$FFFB CTIMER $FFF8-$FFF9 CTIMER $FFF8-$FFF9 CPI $FFF8-$FFF9 TIMER $FFF6-$FFF7 TIMER $FFF6-$FFF7 TIMER $FFF6-$FFF7 TIMER $FFF6-$FFF7 TIMER $FFF6-$FFF7 TIMER $FFF6-$FFF7 TIMER $FFF6-$FFF7 TIMER $FFF6-$FFF7 TIMER $FFF6-$FFF7 TIMER $FFF6-$FFF7 KEYF $FFFA-$FFFB LVI $FFF4-$FFF5 SPI $FFF2-$FFF3 SPI $FFF2-$FFF3 SCI $FFF0-$FFF1 SCI $FFF0-$FFF1 SCI $FFF0-$FFF1 SCI $FFF0-$FFF1 SCI $FFF0-$FFF1 Register Flag name -- -- -- CTCSR CTCSR CPICSR TSR TSR TSR TSR TSR2 TSR2 TSR2 TSR2 TSR TSR2 KEY SOR SPSR SPSR SCSR SCSR SCSR SCSR SCSR -- -- -- CTOF RTIF CPIF ICF1 OCF1 ICF2 OCF2 ICF3 OCF3 ICF4 OCF4 TOF TOF KSF LVI SPIF MODF TDRE TC RDRF IDLE OR Interrupts Reset Software interrupt External interrupt Core timer overflow Real time interrupt Custom periodic interrupt Timer input capture1 Timer output compare1 Timer input capture2 Timer output compare2 Timer input capture3 Timer output compare3 Timer input capture4 Timer output compare4 Timer1 overflow Timer2 overflow Keyboard interrupt Low voltage interrupt SPI request interrupt SPI mode error SCI transmit interrupt SCI transmit complete SCI receive interrupt SCI idle line interrupt SCI overrun error Freescale Semiconductor, Inc... 14.2.3.2 Programmable 16-bit timer interrupt 14 There are ten different timer interrupt flags that cause a timer interrupt whenever they are set and enabled. The timer interrupt enable bits are located in the timer control register (TCR) and the timer interrupt flags are located in the timer status registers (TSR1, TSR2). All three interrupts will vector to the same service routine, whose start address is contained in memory locations $FFF6 and $FFF7. TPG MOTOROLA 14-6 For More Information On This Product, Go to: www.freescale.com RESETS AND INTERRUPTS MC68HC05F32 Freescale Semiconductor, Inc. 14.2.3.3 Keyboard interrupt Freescale Semiconductor, Inc... When configured as input pins, all eight port A lines provide a wired-OR keyboard interrupt facility and will generate an interrupt, provided that the keyboard interrupt enable bit (KIE) in the keyboard/timer register (KEY/TIM) is set. The address of the interrupt service routine is specified by the contents of memory locations $0FFA and $0FFB. Since this interrupt vector is shared with the IRQ external interrupt function the interrupt service routine should check KSF to determine the interrupt source. KSF should be cleared by software in the interrupt service routine. Care must be taken to allow adequate time for switch debounce before clearing the flag. 14.2.3.4 Low voltage interrupt There is a low voltage interrupt flag that causes an interrupt whenever it is set and enabled. The low voltage interrupt enable bit and the interrupt flag are located in the system option register (SOR). This interrupt will vector to the service routine, located at the address specified by the contents of memory locations $FFF4 and $FFF5. 14.2.3.5 Serial peripheral interface (SPI) interrupt An interrupt in the serial peripheral interface (SPI) occurs when one of the interrupt flag bits in the SPI status register SPSR is set, provided the I-bit in the condition code register is clear and the enable bit SPIE in the SPI control register is enabled. The SPI interrupt causes the program to vector to memory location $FFF2 and $FFF3 which contains the starting address of the interrupt service routine. Software in the SPI service routine must determine the priority and cause of the SPI interrupt by examined the interrupt flag bits located in the SPI status register. 14.2.3.6 Serial communications interface (SCI) interrupt There are five different interrupt flags (TDRE, TC, OR, RDRE, IDLE) that will cause an SCI interrupt whenever they are set and enabled. These five interrupt flags are found in the five most significant bits of the SCI status register SCSR. The actual processor interrupt is generated only if the I-bit in the condition code register is clear and the enable bit in the serial communication control register 2 (SCCR2) is enabled. The SCI interrupt causes the program counter to vector to the address pointed to by memory locations $FFF0-$FFF1 which contain the start address of the interrupt service routine. Software in the SCI interrupt service routine must determine the priority and cause of the SCI interrupt by examining the interrupt flags and the status bits in the serial communications status register SCSR. 14 TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com RESETS AND INTERRUPTS MOTOROLA 14-7 Freescale Semiconductor, Inc. 14.2.3.7 Custom periodic interrupt (CPI) There is a timer interrupt flag that causes a CPI interrupt from the 32 kHz clock system whenever set and enabled. The interrupt flag and enable bits are located in the CPI control and status register (CPICSR). An interrupt will vector to the same interrupt service routine as the core timer interrupts, located at the address specified by the contents of memory location $FFF8 and $FFF9. Freescale Semiconductor, Inc... 14.2.4 Hardware controlled interrupt sequence The following three functions (RESET, STOP, and WAIT) are not in the strictest sense interrupts. However, they are acted upon in a similar manner. Flowcharts for STOP and WAIT are shown in Figure 2-1. RESET: A reset condition causes the program to vector to its starting address, which is contained in memory locations $FFFE (MSB) and $FFFF (LSB). The I-bit in the condition code register is also set, to disable interrupts. STOP: The STOP instruction causes the oscillator to be turned off and the processor to `sleep' until an external interrupt (IRQ), a low voltage interrupt (LVI), a custom periodic interrupt (CPI), or a keyboard interrupt occurs, or the device is reset. WAIT: The WAIT instruction causes all processor clocks to stop, but leaves the timer clocks running. This `rest' state of the processor can be cleared by reset, an external interrupt (IRQ), a keyboard interrupt, a timer interrupt (core or 16-bit), or a CPI, SPI, SCI, LVI interrupt. There are no special WAIT vectors for these interrupts. 14 TPG MOTOROLA 14-8 For More Information On This Product, Go to: www.freescale.com RESETS AND INTERRUPTS MC68HC05F32 Freescale Semiconductor, Inc. 15 CPU CORE AND INSTRUCTION SET This section provides a description of the CPU core registers, the instruction set and the addressing modes of the MC68HC05F32. Freescale Semiconductor, Inc... 15.1 Registers The MCU contains five registers, as shown in the programming model of Figure 15-1. The interrupt stacking order is shown in Figure 15-2. 7 7 15 7 0 Accumulator 0 Index register 0 Program counter 15 7 0 0000000011 7 0 111HINZC Stack pointer Condition code register Carry / borrow Zero Negative Interrupt mask Half carry Figure 15-1 Programming model 15 15.1.1 Accumulator (A) The accumulator is a general purpose 8-bit register used to hold operands and results of arithmetic calculations or data manipulations. TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com CPU CORE AND INSTRUCTION SET MOTOROLA 15-1 Freescale Semiconductor, Inc. 7 Increasing memory address Condition code register Accumulator Index register Program counter high Program counter low Return 0 Stack Interrupt Decreasing memory address Unstack Figure 15-2 Stacking order Freescale Semiconductor, Inc... 15.1.2 Index register (X) The index register is an 8-bit register, which can contain the indexed addressing value used to create an effective address. The index register may also be used as a temporary storage area. 15.1.3 Program counter (PC) The program counter is a 16-bit register, which contains the address of the next byte to be fetched. 15.1.4 Stack pointer (SP) The stack pointer is a 16-bit register, which contains the address of the next free location on the stack. During an MCU reset or the reset stack pointer (RSP) instruction, the stack pointer is set to location $00FF. The stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled from the stack. When accessing memory, the ten most significant bits are permanently set to 0000000011. These ten bits are appended to the six least significant register bits to produce an address within the range of $00C0 to $00FF. Subroutines and interrupts may use up to 64 (decimal) locations. If 64 locations are exceeded, the stack pointer wraps around and overwrites the previously stored information. A subroutine call occupies two locations on the stack; an interrupt uses five locations. 15 15.1.5 Condition code register (CCR) The CCR is a 5-bit register in which four bits are used to indicate the results of the instruction just executed, and the fifth bit indicates whether interrupts are masked. These bits can be individually tested by a program, and specific actions can be taken as a result of their state. Each bit is explained in the following paragraphs. TPG MOTOROLA 15-2 For More Information On This Product, Go to: www.freescale.com CPU CORE AND INSTRUCTION SET MC68HC05F32 Freescale Semiconductor, Inc. Half carry (H) This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4. Interrupt (I) When this bit is set, all maskable interrupts are masked. If an interrupt occurs while this bit is set, the interrupt is latched and remains pending until the interrupt bit is cleared. Negative (N) When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative. Zero (Z) When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was zero. Carry/borrow (C) When set, this bit indicates that a carry or borrow out of the arithmetic logical unit (ALU) occurred during the last arithmetic operation. This bit is also affected during bit test and branch instructions and during shifts and rotates. Freescale Semiconductor, Inc... 15.2 Instruction set The MCU has a set of 62 basic instructions. They can be grouped into five different types as follows: - - - - - Register/memory Read/modify/write Branch Bit manipulation Control The following paragraphs briefly explain each type. All the instructions within a given type are presented in individual tables. This MCU uses all the instructions available in the M146805 CMOS family plus one more: the unsigned multiply (MUL) instruction. This instruction allows unsigned multiplication of the contents of the accumulator (A) and the index register (X). The high-order product is then stored in the index register and the low-order product is stored in the accumulator. A detailed definition of the MUL instruction is shown in Table 15-1. 15 TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com CPU CORE AND INSTRUCTION SET MOTOROLA 15-3 Freescale Semiconductor, Inc. 15.2.1 Register/memory Instructions Most of these instructions use two operands. The first operand is either the accumulator or the index register. The second operand is obtained from memory using one of the addressing modes. The jump unconditional (JMP) and jump to subroutine (JSR) instructions have no register operand. Refer to Table 15-2 for a complete list of register/memory instructions. Freescale Semiconductor, Inc... 15.2.2 Branch instructions These instructions cause the program to branch if a particular condition is met; otherwise, no operation is performed. Branch instructions are two-byte instructions. Refer to Table 15-3. 15.2.3 Bit manipulation instructions The MCU can set or clear any writable bit that resides in the first 256 bytes of the memory space (page 0). All port data and data direction registers, timer and serial interface registers, control/status registers and a portion of the on-chip RAM reside in page 0. An additional feature allows the software to test and branch on the state of any bit within these locations. The bit set, bit clear, bit test and branch functions are all implemented with single instructions. For the test and branch instructions, the value of the bit tested is also placed in the carry bit of the condition code register. Refer to Table 15-4. 15.2.4 Read/modify/write instructions These instructions read a memory location or a register, modify or test its contents, and write the modified value back to memory or to the register. The test for negative or zero (TST) instruction is an exception to this sequence of reading, modifying and writing, since it does not modify the value. Refer to Table 15-5 for a complete list of read/modify/write instructions. 15.2.5 Control instructions 15 These instructions are register reference instructions and are used to control processor operation during program execution. Refer to Table 15-6 for a complete list of control instructions. TPG MOTOROLA 15-4 For More Information On This Product, Go to: www.freescale.com CPU CORE AND INSTRUCTION SET MC68HC05F32 Freescale Semiconductor, Inc. 15.2.6 Tables Tables for all the instruction types listed above follow. In addition there is a complete alphabetical listing of all the instructions (see Table 15-7), and an opcode map for the instruction set of the M68HC05 MCU family (see Table 15-8). Table 15-1 MUL instruction Operation Description X:A X*A Multiplies the eight bits in the index register by the eight bits in the accumulator and places the 16-bit result in the concatenated accumulator and index register. H : Cleared I : Not affected N : Not affected Z : Not affected C : Cleared MUL Addressing mode Cycles Bytes Opcode Inherent 11 1 $42 Freescale Semiconductor, Inc... Condition codes Source Form 15.3 Addressing modes Ten different addressing modes provide programmers with the flexibility to optimize their code for all situations. The various indexed addressing modes make it possible to locate data tables, code conversion tables and scaling tables anywhere in the memory space. Short indexed accesses are single byte instructions; the longest instructions (three bytes) enable access to tables throughout memory. Short absolute (direct) and long absolute (extended) addressing are also included. One or two byte direct addressing instructions access all data bytes in most applications. Extended addressing permits jump instructions to reach all memory locations. The term `effective address' (EA) is used in describing the various addressing modes. The effective address is defined as the address from which the argument for an instruction is fetched or stored. The ten addressing modes of the processor are described below. Parentheses are used to indicate `contents of' the location or register referred to. For example, (PC) indicates the contents of the location pointed to by the PC (program counter). An arrow indicates `is replaced by' and a colon indicates concatenation of two bytes. For additional details and graphical illustrations, refer to the M6805 HMOS/M146805 CMOS Family Microcomputer/ Microprocessor User's Manual or to the M68HC05 Applications Guide. 15 TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com CPU CORE AND INSTRUCTION SET MOTOROLA 15-5 Freescale Semiconductor, Inc. Table 15-2 Register/memory instructions Addressing modes Immediate Mnemonic Direct Extended Indexed (no offset) # Cycles # Cycles Opcode # Bytes Indexed (8-bit offset) # Cycles Opcode # Bytes Indexed (16-bit offset) # Cycles 5 5 3 3 3 3 3 3 3 3 3 3 3 3 3 3 5 5 5 5 5 5 5 5 5 5 4 7 6 6 TPG # Cycles # Cycles Opcode Opcode Opcode Opcode D6 DE D7 DF DB D9 D0 D2 D4 DA D8 D1 D3 D5 DC DD 3 3 # Bytes # Bytes # Bytes Function Load A from memory Load X from memory Store A in memory Store X in memory Add memory to A Add memory and carry to A Subtract memory Subtract memory from A with borrow AND memory with A OR memory with A Exclusive OR memory with A Arithmetic compare A with memory Arithmetic compare X with memory Bit test memory with A (logical compare) Jump unconditional Jump to subroutine Freescale Semiconductor, Inc... LDA LDX STA STX ADD ADC SUB SBC AND ORA EOR CMP CPX BIT JMP JSR A6 AE 2 2 2 2 B6 BE B7 BF 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 4 4 3 3 3 3 3 3 3 3 3 3 2 5 C6 CE C7 CF CB C9 C0 C2 C4 CA C8 C1 C3 C5 CC CD 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 5 5 4 4 4 4 4 4 4 4 4 4 3 6 F6 FE F7 FF FB F9 F0 F2 F4 FA F8 F1 F3 F5 FC FD 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 3 4 4 3 3 3 3 3 3 3 3 3 3 2 5 E6 EE E7 EF EB E9 E0 E2 E4 EA E8 E1 E3 E5 EC ED 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 4 4 5 5 4 4 4 4 4 4 4 4 4 4 3 6 AB A9 A0 A2 A4 AA A8 A1 A3 A5 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 BB B9 B0 B2 B4 BA B8 B1 B3 B5 BC BD 15.3.1 Inherent In the inherent addressing mode, all the information necessary to execute the instruction is contained in the opcode. Operations specifying only the index register or accumulator, as well as the control instruction, with no other arguments are included in this mode. These instructions are one byte long. 15 15.3.2 Immediate In the immediate addressing mode, the operand is contained in the byte immediately following the opcode. The immediate addressing mode is used to access constants that do not change during program execution (e.g. a constant used to initialize a loop counter). EA = PC+1; PC PC+2 MOTOROLA 15-6 For More Information On This Product, Go to: www.freescale.com CPU CORE AND INSTRUCTION SET MC68HC05F32 # Bytes Freescale Semiconductor, Inc. Table 15-3 Branch instructions Relative addressing mode Opcode # Bytes # Cycles 20 2 3 21 2 3 22 2 3 23 2 3 24 2 3 24 2 3 25 2 3 25 2 3 26 2 3 27 2 3 28 2 3 29 2 3 2A 2 3 2B 2 3 2C 2 3 2D 2 3 2E 2 3 2F 2 3 AD 2 6 Function Branch always Branch never Branch if higher Branch if lower or same Branch if carry clear (Branch if higher or same) Branch if carry set (Branch if lower) Branch if not equal Branch if equal Branch if half carry clear Branch if half carry set Branch if plus Branch if minus Branch if interrupt mask bit is clear Branch if interrupt mask bit is set Branch if interrupt line is low Branch if interrupt line is high Branch to subroutine Freescale Semiconductor, Inc... Mnemonic BRA BRN BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BHCC BHCS BPL BMI BMC BMS BIL BIH BSR Table 15-4 Bit manipulation instructions Addressing modes Bit set/clear Bit test and branch Opcode # Bytes # Cycles Opcode # Bytes # Cycles 2*n 3 5 01+2*n 3 5 10+2*n 2 5 11+2*n 2 5 Function Branch if bit n is set Branch if bit n is clear Set bit n Clear bit n Mnemonic BRSET n (n=0-7) BRCLR n (n=0-7) BSET n (n=0-7) BCLR n (n=0-7) 15.3.3 Direct 15 EA = (PC+1); PC PC+2 Address bus high 0; Address bus low (PC+1) In the direct addressing mode, the effective address of the argument is contained in a single byte following the opcode byte. Direct addressing allows the user to directly address the lowest 256 bytes in memory with a single two-byte instruction. TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com CPU CORE AND INSTRUCTION SET MOTOROLA 15-7 Freescale Semiconductor, Inc. Table 15-5 Read/modify/write instructions Addressing modes Inherent (A) Mnemonic # Cycles Opcode Inherent (X) # Cycles Opcode Opcode Direct Indexed (no offset) # Cycles # Cycles Opcode # Bytes Indexed (8-bit offset) # Cycles TPG Opcode # Bytes # Bytes # Bytes Function Increment Decrement Clear Complement Negate (two's complement) Rotate left through carry Rotate right through carry Logical shift left Logical shift right Arithmetic shift right Test for negative or zero Multiply Freescale Semiconductor, Inc... INC DEC CLR COM NEG ROL ROR LSL LSR ASR TST MUL 4C 4A 4F 43 40 49 46 48 44 47 4D 42 1 3 5C 1 3 5A 1 3 5F 1 3 53 1 3 50 1 3 59 1 3 56 1 3 58 1 3 54 1 3 57 1 3 5D 1 11 1 3 3C 1 3 3A 1 3 3F 1 3 33 1 3 30 1 3 39 1 3 36 1 3 38 1 3 34 1 3 37 1 3 3D 2 5 7C 2 5 7A 2 5 7F 2 5 73 2 5 70 2 5 79 2 5 76 2 5 78 2 5 74 2 5 77 2 4 7D 1 5 6C 1 5 6A 1 5 6F 1 5 63 1 5 60 1 5 69 1 5 66 1 5 68 1 5 64 1 5 67 1 4 6D 26 26 26 26 26 26 26 26 26 26 25 Table 15-6 Control instructions Inherent addressing mode Opcode # Bytes # Cycles 97 1 2 9F 1 2 99 1 2 98 1 2 9B 1 2 9A 1 2 83 1 10 81 1 6 80 1 9 9C 1 2 9D 1 2 8E 1 2 8F 1 2 15 Function Transfer A to X Transfer X to A Set carry bit Clear carry bit Set interrupt mask bit Clear interrupt mask bit Software interrupt Return from subroutine Return from interrupt Reset stack pointer No-operation Stop Wait Mnemonic TAX TXA SEC CLC SEI CLI SWI RTS RTI RSP NOP STOP WAIT MOTOROLA 15-8 For More Information On This Product, Go to: www.freescale.com CPU CORE AND INSTRUCTION SET MC68HC05F32 # Bytes Freescale Semiconductor, Inc. Table 15-7 Instruction set Addressing modes EXT REL IX IX1 Condition codes I NZC * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 0 * * * * 01 * * Mnemonic ADC ADD AND ASL ASR BCC BCLR BCS BEQ BHCC BHCS BHI BHS BIH BIL BIT BLO BLS BMC BMI BMS BNE BPL BRA BRN BRCLR BRSET BSET BSR CLC CLI CLR CMP INH IMM DIR IX2 BSC BTB H * * * * * * * * * * * * * * * * * * * * * * * 0 * * Freescale Semiconductor, Inc... 15 Condition code symbols Address mode abbreviations BSC Bit set/clear BTB Bit test & branch DIR INH Direct Inherent EXT Extended IMM IX IX1 IX2 REL Immediate Indexed (no offset) Indexed, 1 byte offset Indexed, 2 byte offset Relative H I N Z C Half carry (from bit 3) Interrupt mask Negate (sign bit) Zero Carry/borrow * ? 0 1 Tested and set if true, cleared otherwise Not affected Load CCR from stack Cleared Set Not implemented TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com CPU CORE AND INSTRUCTION SET MOTOROLA 15-9 Freescale Semiconductor, Inc. Table 15-7 Instruction set (Continued) Addressing modes EXT REL IX IX1 Condition codes I NZC * * 1 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 0 0 * * * 0 * * * * * * * * * * * * * * * * * * * ????? * * * * * * * * * * * 1 * 1 * * * * * * * 0 * * * * * * * * * 1 * * * * * * * * * * * * * * * * * 0 * * * Mnemonic COM CPX DEC EOR INC JMP JSR LDA LDX LSL LSR MUL NEG NOP ORA ROL ROR RSP RTI RTS SBC SEC SEI STA STOP STX SUB SWI TAX TST TXA WAIT INH IMM DIR IX2 BSC BTB H Freescale Semiconductor, Inc... 15 Condition code symbols Address mode abbreviations BSC Bit set/clear BTB Bit test & branch DIR INH Direct Inherent EXT Extended IMM IX IX1 IX2 REL Immediate Indexed (no offset) Indexed, 1 byte offset Indexed, 2 byte offset Relative H I N Z C Half carry (from bit 3) Interrupt mask Negate (sign bit) Zero Carry/borrow * ? 0 1 Tested and set if true, cleared otherwise Not affected Load CCR from stack Cleared Set Not implemented TPG MOTOROLA 15-10 For More Information On This Product, Go to: www.freescale.com CPU CORE AND INSTRUCTION SET MC68HC05F32 Freescale Semiconductor, Inc... Control High High Low 3 IX 3 3 Low Bit manipulation BTB BSC 0 1 0000 0001 DIR 3 0011 NEG DIR 1 INH 1 INH 2 IX1 1 IX 1 5 Branch REL 2 0010 INH 4 0100 NEGA RTS 1 INH 2 INH 6 2 3 Read/modify/write INH IX1 5 6 0101 0110 IX 7 0111 6 INH 8 1000 5 INH 9 1001 9 IMM A 1010 SUB CMP SBC 2 IMM 2 2 IMM 2 2 2 DIR B 1011 SUB CMP SBC CPX AND BIT LDA STA 2 DIR 3 4 DIR 3 3 DIR 3 3 DIR 3 3 DIR 3 3 DIR 3 3 DIR 3 3 3 Register/memor y EXT IX2 C D 1100 1101 IX1 E 1110 5 IX F 1111 4 MC68HC05F32 NEGX CMP SBC CPX AND BIT LDA STA EOR DIR 3 3 DIR 3 3 EXT 3 4 EXT 3 4 EXT 3 4 EXT 3 4 EXT 3 4 EXT 3 4 3 BRSET0 CMP SBC CPX AND BIT LDA EXT 3 5 IX2 2 5 IX2 2 5 IX2 2 5 IX2 2 5 IX2 2 5 5 BSET0 CMP SBC CPX AND BIT IX2 2 5 IX1 1 4 IX1 1 4 5 BRA CMP SBC IX1 1 4 IX1 1 4 IX1 1 4 NEG NEG RTI SUB 4 SUB SUB SUB 3 BRCLR0 MUL 1 11 BTB 2 5 BCLR0 BSC 2 5 BRN REL 2 3 3 BRSET1 COM LSR DIR 1 INH 1 INH 2 IX1 1 IX 2 DIR 1 5 5 BTB 2 5 INH 3 BSET1 COMA LSRA BIT 2 IMM 2 2 INH 1 3 BSC 2 5 BHI COMX LSRX INH 2 3 3 REL 3 IX 3 3 BRCLR1 LSR IX1 1 6 BTB 2 5 BCLR1 LSR IX 1 5 INH 2 BSC 2 5 BLS AND IMM 2 2 REL 3 COM 6 COM 5 SWI 10 CPX IMM 2 2 CPX AND BIT LDA IX1 1 4 IX 3 IX 3 IX 3 3 BRSET2 BTB 2 5 BSET2 BSC 2 5 BCC REL 2 3 3 BRCLR2 ROR ASR LSL ROL DEC DIR 1 INH 1 INH 2 IX1 1 IX 1 DIR 1 5 DIR 1 5 DIR 1 5 DIR 1 5 5 BTB 2 5 BCLR2 RORA ASRA LSLA ROLA DECA SEI 1 INH 2 2 INH 1 3 INH 1 3 INH 1 3 INH 1 3 3 BSC 2 5 BCS RORX ASRX LSLX ROLX DECX ADD INH 2 3 INH 2 3 INH 2 3 INH 2 3 3 REL 2 3 3 BRSET3 ASR LSL ROL DEC IX1 1 6 IX1 1 6 IX1 1 6 IX1 1 6 BTB 2 5 BSET3 ASR LSL ROL DEC IX 5 1 IX 5 1 IX 5 1 IX 5 2 IMM 2 BSC 2 5 BNE TAX CLC SEC CLI INH 2 2 INH 2 2 INH 2 2 REL 3 ROR 6 ROR 5 LDA IMM 2 2 LDA STA EXT 3 4 EXT 3 4 IX2 2 6 IX 3 IX1 1 5 IX 4 3 BRCLR3 EOR ADC ORA IMM 2 2 IMM 2 2 IMM 2 IMM 2 2 2 BTB 2 5 DIR 3 3 BCLR3 EOR ADC ORA ADD JMP INH 2 INH 2 2 BSC 2 5 BEQ REL 2 3 STA EOR ADC ORA ADC EXT 3 4 IX2 2 5 IX2 2 5 IX2 2 5 STA EOR ADC ORA ORA IX1 1 4 IX1 1 4 IX1 1 4 3 BRSET4 BTB 2 5 BSET4 BSC 2 5 BHCC REL 2 3 EOR ADC ORA DIR 3 3 EXT 3 4 IX2 2 5 IX1 1 4 IX 3 IX 3 IX 3 IX 3 3 BRCLR4 BTB 2 5 BCLR4 BSC 2 5 BHCS REL 2 3 3 BRSET5 BTB 2 5 BSET5 BSC 2 5 BPL REL 2 3 3 BRCLR5 INC TST DIR 1 INH 1 INH 2 IX1 1 IX 1 DIR 1 4 5 BTB 2 5 BCLR5 INCA TSTA STOP 1 2 2 INH 1 3 3 BSC 2 5 BMI INCX TSTX INH 2 3 3 REL 2 3 ADD DIR 3 2 ADD JMP BSR LDX 6 REL 2 2 IMM 2 EXT 3 3 DIR 3 5 EXT 3 6 ADD JMP JSR LDX JSR DIR 3 3 IX2 2 4 IX2 2 7 ADD JMP JSR LDX EXT 3 4 IX1 1 3 IX1 1 6 3 BRSET6 TST IX1 1 5 BTB 2 5 BSET6 TST IX 4 1 BSC 2 5 BMC NOP REL 3 INC 6 INC 5 RSP INH 2 2 JMP JSR LDX IX2 2 5 IX 2 IX 5 3 BRCLR6 BTB 2 5 BCLR6 BSC 2 5 BMS REL 2 3 JSR LDX IX1 1 4 3 BRSET7 CLR DIR 1 INH 1 INH 2 IX1 1 IX 1 5 BTB 2 5 BSET7 CLRA 3 BSC 2 5 BIL CLRX 3 REL 2 3 LDX INH 2 INH 1 IX 3 Table 15-8 M68HC05 opcode map 3 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com CLR 6 CPU CORE AND INSTRUCTION SET CLR 5 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111 WAIT TXA 2 INH 2 BRCLR7 BTB 2 5 BCLR7 BSC 2 5 BIH REL 3 STX DIR 3 4 DIR 3 STX EXT 3 5 EXT 3 STX IX2 2 6 IX2 2 STX IX1 1 5 IX1 1 STX IX 4 IX 3 BTB 2 BSC 2 REL 2 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111 Abbreviations for address modes and register s Legend F 1111 Mnemonic 1 Opcode in hexadecimal Opcode in binary SUB Not implemented Bytes Cycles Address mode 3 IX BSC BTB DIR EXT INH IMM IX IX1 IX2 REL A X Indexed (no offset) Indexed, 1 byte (8-bit) offset Indexed, 2 byte (16-bit) offset Relative Accum ulator Index register Bit set/clear Bit test and branch Direct Extended Inherent Immediate 0 0000 TPG MOTOROLA 15-11 15 Freescale Semiconductor, Inc. 15.3.4 Extended In the extended addressing mode, the effective address of the argument is contained in the two bytes following the opcode byte. Instructions with extended addressing mode are capable of referencing arguments anywhere in memory with a single three-byte instruction. When using the Motorola assembler, the user need not specify whether an instruction uses direct or extended addressing. The assembler automatically selects the short form of the instruction. EA = (PC+1):(PC+2); PC PC+3 Address bus high (PC+1); Address bus low (PC+2) Freescale Semiconductor, Inc... 15.3.5 Indexed, no offset In the indexed, no offset addressing mode, the effective address of the argument is contained in the 8-bit index register. This addressing mode can access the first 256 memory locations. These instructions are only one byte long. This mode is often used to move a pointer through a table or to hold the address of a frequently referenced RAM or I/O location. EA = X; PC PC+1 Address bus high 0; Address bus low X 15.3.6 Indexed, 8-bit offset In the indexed, 8-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit index register and the unsigned byte following the opcode. Therefore the operand can be located anywhere within the lowest 511 memory locations. This addressing mode is useful for selecting the mth element in an n element table. EA = X+(PC+1); PC PC+2 Address bus high K; Address bus low X+(PC+1) where K = the carry from the addition of X and (PC+1) 15.3.7 Indexed, 16-bit offset 15 In the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit index register and the two unsigned bytes following the opcode. This address mode can be used in a manner similar to indexed, 8-bit offset except that this three-byte instruction allows tables to be anywhere in memory. As with direct and extended addressing, the Motorola assembler determines the shortest form of indexed addressing. EA = X+[(PC+1):(PC+2)]; PC PC+3 Address bus high (PC+1)+K; Address bus low X+(PC+2) where K = the carry from the addition of X and (PC+2) TPG MOTOROLA 15-12 For More Information On This Product, Go to: www.freescale.com CPU CORE AND INSTRUCTION SET MC68HC05F32 Freescale Semiconductor, Inc. 15.3.8 Relative The relative addressing mode is only used in branch instructions. In relative addressing, the contents of the 8-bit signed byte (the offset) following the opcode are added to the PC if, and only if, the branch conditions are true. Otherwise, control proceeds to the next instruction. The span of relative addressing is from -126 to +129 from the opcode address. The programmer need not calculate the offset when using the Motorola assembler, since it calculates the proper offset and checks to see that it is within the span of the branch. EA = PC+2+(PC+1); PC EA if branch taken; otherwise EA = PC PC+2 Freescale Semiconductor, Inc... 15.3.9 Bit set/clear In the bit set/clear addressing mode, the bit to be set or cleared is part of the opcode. The byte following the opcode specifies the address of the byte in which the specified bit is to be set or cleared. Any read/write bit in the first 256 locations of memory, including I/O, can be selectively set or cleared with a single two-byte instruction. EA = (PC+1); PC PC+2 Address bus high 0; Address bus low (PC+1) 15.3.10 Bit test and branch The bit test and branch addressing mode is a combination of direct addressing and relative addressing. The bit to be tested and its condition (set or clear) is included in the opcode. The address of the byte to be tested is in the single byte immediately following the opcode byte (EA1). The signed relative 8-bit offset in the third byte (EA2) is added to the PC if the specified bit is set or cleared in the specified memory location. This single three-byte instruction allows the program to branch based on the condition of any readable bit in the first 256 locations of memory. The span of branch is from -125 to +130 from the opcode address. The state of the tested bit is also transferred to the carry bit of the condition code register. EA1 = (PC+1); PC PC+2 Address bus high 0; Address bus low (PC+1) EA2 = PC+3+(PC+2); PC EA2 if branch taken; otherwise PC PC+3 15 TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com CPU CORE AND INSTRUCTION SET MOTOROLA 15-13 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... THIS PAGE LEFT BLANK INTENTIONALLY 15 TPG MOTOROLA 15-14 For More Information On This Product, Go to: www.freescale.com CPU CORE AND INSTRUCTION SET MC68HC05F32 Freescale Semiconductor, Inc. 16 ELECTRICAL SPECIFICATIONS This section contains the electrical specifications and associated timing information for the MC68HC05F32. Freescale Semiconductor, Inc... 16.1 Maximum ratings Table 16-1 Maximum ratings Rating (1) Supply voltage Input voltage Bootloader mode (IRQ pin only) Current drain per pin(2) -- excluding VDD and VSS Operating temperature range -- standard -- extended Storage temperature range Symbol V DD VIN V IN I TA T STG Value - 0.3 to + 0.7 V SS - 0.3 to VSS + 0.3 V SS - 0.3 to 2 x VDD + 0.3 25 TL to TH 0 to + 70 -40 to + 85 - 65 to + 150 Unit V V V mA C C (1) All voltages are with respect to V . SS (2) Maximum current drain per pin is for one pin at a time, limited by an external resistor. Note: This device contains circuitry designed to protect against damage due to high electrostatic voltages or electric fields. However, it is recommended that normal precautions be taken to avoid the application of any voltages higher than those given in the Maximum Ratings table to this high impedance circuit. For maximum reliability all unused inputs should be tied to either VSS or VDD. 16 TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com ELECTRICAL SPECIFICATIONS MOTOROLA 16-1 Freescale Semiconductor, Inc. 16.2 Thermal characteristics and power considerations Table 16-2 Package thermal characteristics Characteristics Thermal resistance -- 100-pin QFP package -- 80-pin QFP package Symbol JA Value 55 Unit C/W Freescale Semiconductor, Inc... The average chip junction temperature, TJ, in degrees Celsius can be obtained from the following equation: T J = T A + ( P D * JA ) where: TA = Ambient Temperature (C) JA = Package Thermal Resistance, Junction-to-ambient (C/W) PD = PINT + PI/O (W) PINT = Internal Chip Power = IDD * VDD (W) PI/O = Power Dissipation on Input and Output pins (User determined) An approximate relationship between PD and TJ (if PI/O is neglected) is: K P D = --------------------T J + 273 Solving equations [1] and [2] for K gives: K = P D * ( T A + 273 ) + JA * P D2 where K is a constant for a particular part. K can be determined by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained for any value of TA by solving the above equations. The package thermal characteristics are shown in Table 16-2. 16 TPG MOTOROLA 16-2 For More Information On This Product, Go to: www.freescale.com ELECTRICAL SPECIFICATIONS MC68HC05F32 Freescale Semiconductor, Inc. 16.3 DC electrical characteristics Table 16-3 DC electrical characteristics (VDD = 5.0 V) (VDD = 5.0VDC 10%, V SS = 0 VDC , TA = -40C to +85C, unless otherwise stated) Characteristic Symbol Min. Typ. (1) Max. Output voltage ILOAD = -10 A VOH V DD - 0.1 -- -- ILOAD = +10 A VOL -- -- 0.1 Output high voltage (ILOAD = -0.8 mA) VOH V DD - 0.8 -- -- Ports (PA0-7, PB0-7, PC0-7, PH0-7, PI7-0) Output low voltage (ILOAD = +1.6 mA) Ports(PA0-7, PB0-7, PC4-7, PD4-7, PE4-7, VOL -- -- 0.4 PH0-7, PI0-7, PJ0-7) Input high voltage V IH 0.7V DD -- 15.0 Ports (PD0-7, PE0-7) Input high voltage Ports (PA0-7, PB0-7, PC0-7, PF0-7, PG0-7) V IH 0.7V DD -- V DD IRQ, RESET,OSC1, OSC3 Input low voltage Ports (PA0-7, PB0-7, PC0-7, PF0-7, PG0-7) V IL -- -- 0.2V DD IRQ, RESET, OSC1, OSC3 Supply Current (2) IDD RUN -- 5 10 WAIT -- 0.6 1.2 STOP -- -- 80 I/O ports hi-Z leakage current -- -- 10 IOZ Ports (PA0-7, PB0-7, PC0-7, PD0-7, PE0-7) Input current IIN -- -- 1 RESET, IRQ, OSC1 Capacitance Ports (as input or output) C OUT -- -- 12 RESET, IRQ C IN -- -- 8 Input current low IIL - 30 - 90 - 170 Ports (PA0-7, PB0-7, PC0-7), RESET LCD step down resistor R LCDSD -- 20 -- (1) Typical values are at midpoint of voltage range and at 25C only. (2) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the transient switching currents inherent in CMOS designs. RUN and WAIT IDD : measured using an external square-wave clock source (fOSC = 3.58 MHz); all inputs0.2V from rail; no DC loads; maximum load on outputs 50pF (20pF on OSC2). WAIT I DD : only the timer system active; current varies linearly with the OSC2 capacitance. STOP and WAIT I DD : all ports configured as inputs, V = 0.2 V, VIH = VDD - 0.2 V. STOP IDD : IL measured with OSC1 = V SS . Unit V V V V V V Freescale Semiconductor, Inc... V mA mA A A A pF pF A k 16 TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com ELECTRICAL SPECIFICATIONS MOTOROLA 16-3 Freescale Semiconductor, Inc. Table 16-4 DC electrical characteristics (VDD = 2.7 V) (VDD = 2.7VDC min, VSS = 0 VDC , TA = -40C to +85C, unless otherwise stated) Characteristic Symbol Min. Output voltage ILOAD = -10 A VOH V DD - 0.1 ILOAD = +10 A VOL -- Output high voltage (ILOAD = -0.8 mA) VOH V DD - 0.3 Ports (PA0-7, PB0-7, PC0-7, PH0-7, PI7-0) Output low voltage (ILOAD = +1.6 mA) Ports(PA0-7, PB0-7, PC4-7, PD4-7, PE4-7, VOL -- PH0-7, PI0-7, PJ0-7) Input high voltage V IH 0.7V DD Ports (PD0-7, PE0-7) Input high voltage Ports (PA0-7, PB0-7, PC0-7, PF0-7, PG0-7) V IH 0.7V DD IRQ, RESET,OSC1, OSC3 Input low voltage Ports (PA0-7, PB0-7, PC0-7, PF0-7, PG0-7) V IL -- IRQ, RESET, OSC1, OSC3 Supply Current (2) IDD RUN -- WAIT -- STOP -- I/O ports hi-Z leakage current -- IOZ Ports (PA0-7, PB0-7, PC0-7, PD0-7, PE0-7) Input current IIN -- RESET, IRQ, OSC1 Capacitance Ports (as input or output) C OUT -- RESET, IRQ C IN -- Input current low IIL -5 Ports (PA0-7, PB0-7, PC0-7), RESET LCD step down resistor R LCDSD -- (1) Typical values are at midpoint of voltage range and at 25C only. (2) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the transient switching currents inherent in CMOS designs. RUN and WAIT IDD : measured using an external square-wave clock source (fOSC = 3.58 MHz); all inputs0.2V from rail; no DC loads; maximum load on outputs 50pF (20pF on OSC2). WAIT I DD : only the timer system active; current varies linearly with the OSC2 capacitance. STOP and WAIT I DD : all ports configured as inputs, V = 0.2 V, VIH = VDD - 0.2 V. STOP IDD : IL measured with OSC1 = V SS . Typ. (1) -- -- -- -- -- -- Max. -- 0.1 -- 0.3 15.0 V DD Unit V V V V V V Freescale Semiconductor, Inc... -- 0.2V DD V 1.8 0.2 -- -- -- -- -- - 15 20 3.0 1.0 40 10 1 12 8 40 -- mA mA A A A pF pF A k 16 TPG MOTOROLA 16-4 For More Information On This Product, Go to: www.freescale.com ELECTRICAL SPECIFICATIONS MC68HC05F32 Freescale Semiconductor, Inc. 16.4 Control timing Table 16-5 Control timing (VDD = 5V) (VDD = 5.0 VDC 10%, V SS = 0 VDC , TA = TL to TH ) Characteristic Symbol Frequency of operation: Crystal fOSC External clock Internal operating frequency: Crystal fOP External clock Processor cycle time tCYC Stop recovery start-up time tILCH Crystal oscillator start-up time t OXOV RESET pulse width tRL Interrupt pulse width low (edge-triggered) t ILIH Interrupt pulse period tILIL OSC1 pulse width t OH , tOL RC oscillator stabilization time t RCON A/D on current stabilization time t ADON EEPROM byte programming time t EPGM EEPROM byte erase time t EBYTE EEPROM block erase time t EBLOCK EEPROM bulk erase time t EBULK EEPROM programming voltage fall time t FPV EEPROM minimum programming voltage V CCMIN Min. -- DC -- DC 550.0 -- -- 1.5 250.0 (1) Max. 3.579 3.579 1.789 1.789 -- 20.0 20.0 -- -- -- -- 5.0 100.0 15.0 15.0 100.0 300.0 10.0 Unit MHz Freescale Semiconductor, Inc... MHz ns ms ms t CYC ns t CYC ns s s ms ms ms ms s V 100.0 -- -- -- -- -- -- -- 2.7 (1) The minimum period T ILIL should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 CYC . t 16 TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com ELECTRICAL SPECIFICATIONS MOTOROLA 16-5 Freescale Semiconductor, Inc. Table 16-6 Control timing (VDD = 2.7V) (VDD = 2.7 VDC min, VSS = 0 VDC , TA = TL to TH ) Characteristic Frequency of operation: Crystal External clock Internal operating frequency: Crystal External clock Processor cycle time Stop recovery start-up time Crystal oscillator start-up time RESET pulse width Interrupt pulse width low (edge-triggered) Interrupt pulse period OSC1 pulse width RC oscillator stabilization time A/D on current stabilization time EEPROM byte programming time EEPROM byte erase time EEPROM block erase time EEPROM bulk erase time EEPROM programming voltage fall time EEPROM minimum programming voltage Symbol fOSC Min. -- DC -- DC 550.0 -- -- 1.5 250.0 (1) Max. 3.579 3.579 1.789 1.789 -- 20.0 20.0 -- -- -- -- 10.0 200.0 15.0 15.0 100.0 300.0 10.0 Unit MHz Freescale Semiconductor, Inc... fOP tCYC tILCH t OXOV tRL t ILIH tILIL t OH , tOL t RCON t ADON t EPGM t EBYTE t EBLOCK t EBULK t FPV V CCMIN MHz ns ms ms t CYC ns t CYC ns s s ms ms ms ms s V 100.0 -- -- -- -- -- -- -- 2.7 (1) The minimum period T ILIL should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 CYC . t 16 TPG MOTOROLA 16-6 For More Information On This Product, Go to: www.freescale.com ELECTRICAL SPECIFICATIONS MC68HC05F32 Freescale Semiconductor, Inc. 16.5 DC levels for low voltage RESET and LVI Table 16-7 DC levels for low voltage reset and LVI (TA = -40C to +85C, unless otherwise stated) Characteristic Symbol Min. Typ. Power-on reset voltage V RON 2.55 2.8 Power-off reset voltage VROFF 2.45 2.7 Low voltage interrupt VLVI 2.75 3.0 Freescale Semiconductor, Inc... Max. 3.05 2.95 3.25 Unit V V V 16.6 Electrical specifications for DTMF/melody generator Table 16-8 Sine wave tones at TNO Characteristic Operating voltage Tone output level: Low group - row High group - column Frequency deviation (DTMF) Frequency deviation (Melody) Tone output DC level High group pre-emphasis Total harmonic distortion Min. 2.7 0.120 0.160 - 0.65 - 1.5 0.45 1 -- Typ. -- 0.160 0.205 Max. 5.5 0.210 0.280 + 0.65 + 1.5 0.55 3 -- Unit V V rms V rms % % Vdd dB dB 0.50 2.15 -25 Table 16-9 Square wave tones at TNO Characteristic Operating voltage Tone output level: Low group - row High group - column Frequency deviation (Melody) Tone output DC level (+ 1/2 Vp-p value) Min. 2.7 -- -- - 1.5 0.45 Typ. -- 0.270 0.360 0.50 + 1.5 0.55 Max. 5.5 Unit V V p-p V p-p % Vdd 16 TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com ELECTRICAL SPECIFICATIONS MOTOROLA 16-7 Freescale Semiconductor, Inc. Table 16-10 TONEX at TNX output Characteristic Operating voltage Tone output level (square wave) Frequency deviation Min. 2.7 - 1.5 Typ. -- VDD Max. 5.5 + 1.5 Unit V V p-p % Freescale Semiconductor, Inc... 16.7 EEPROM additional information Table 16-11 EEPROM additional information Read/write cycles 10 000 35 000 100 000 Temperature 0 C - 85 C 50 C 25 C Remarks The value is regularly tested and monitored This value is predicted from the tested ones This value is predicted from the tested ones 16.8 PWM timing Table 16-12 PWM timing Characteristic PWM rise time PWM fall time Symbol t PWMR tPWMF Min. 15.0 15.0 Max. 35.0 35.0 Unit ns ns 16 MOTOROLA 16-8 For More Information On This Product, Go to: www.freescale.com ELECTRICAL SPECIFICATIONS MC68HC05F32 Freescale Semiconductor, Inc. 16.9 A/D converter characteristics Table 16-13 A/D converter characteristics (VDD = 5.0 VDC 10%, V SS = 0 VDC , TA = -40C to +85C, unless otherwise stated) Characteristic Parameter Min. Max. Resolution Number of bits resolved by the A/D 8 -- Maximum deviation from the best straight Non-linearity line through A/D transfer characteristics -- 1/2 (AV SS =V RH = VDD, AVSS = VSS ) Quantization error Uncertainty due to converter resolution -- 1/2 Difference between the actual input Absolute accuracy voltage and the full scale equivalent of -- 1 the binary output code for all errors Conversion range Analog input voltage range AV SS V RH V RH Maximum analog reference voltage AV SS V DD + 0.1 AV SS Analog supply voltage VSS - 0.1 -- Total time to perform a single analog to digital conversion Conversion time a. External clock -- 32 b. internal RC oscillator -- 32 Conversion result never decreases with Monotinicity an increase in input voltage and has no GUARANTEED missing codes Zero input reading Conversion result when VIN = AVSS 00 Full scale reading Conversion result when VIN = VRH -- FF Analog input acquisition sampling -- 12 Sample acquisition time(1) a. External clock b. Internal RC oscillator -- 12 Sample/hold capacitance Input leakage AV DD Input capacitance on AN0-AN7 Input leakage on AN0-AN7 Input leakage on VRH Analog supply voltage -- -- -- 12 10 1 1.125V RH Unit bit LSB LSB LSB V V V Freescale Semiconductor, Inc... tCYC s Hex Hex tCYC s pF A A V (1) Source impedances greater than 10 k will adversely affect internal RC charging time during input sampling. (2) The external system error caused by input leakage current is approximately equal to the product of R source and input current. (3) A/D accuracy may decrease as V RH is reduced below 4V. 16 MC68HC05F32 For More Information On This Product, Go to: www.freescale.com ELECTRICAL SPECIFICATIONS MOTOROLA 16-9 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... THIS PAGE LEFT BLANK INTENTIONALLY 16 MOTOROLA 16-10 For More Information On This Product, Go to: www.freescale.com ELECTRICAL SPECIFICATIONS MC68HC05F32 Freescale Semiconductor, Inc. 17 MECHANICAL DATA 17.1 100-pin QFP pinout for the MC68HC05F32 Freescale Semiconductor, Inc... AVDD PD0/AN0 PD1/AN1 PD2/AN2 PD3/AN3 PD4/AN4 PD5/AN5 PD6/AN6 PD7/AN7 AVSS PE0/TCAP1 PE1/TCMP1 PE2/TCAP2 PE3/TCMP2 PE4/REFRESH PE5/PWM1 PE6/PWM2 PE7/PWM3 PC0/TCAP3 PC1/TCAP4 PC2/RDI PC3/TDO PC4/MISO VDD VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VRH PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 OSC1 OSC2 IRQ VSS VDD RESET PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PH7/FP39 PH6/FP38 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PH1/FP33 PH0/FP32 PG7/FP31 PG6/FP30 PG5/FP29 PG4/FP28 PG3/FP27 PG2/FP26 PG1/FP25 PG0/FP24 PH5/FP37 PH4/FP36 PH3/FP35 PH2/FP34 PF7/FP23 PF6/FP22 PF5/FP21 PF4/FP20 PF3/FP19 PF2/FP18 PF1/FP17 PF0/FP16 PI7/FP15 PI6/FP14 PI5/FP13 PC5/MOSI PC6/SCK PC7/SS OSC3 OSC4 TNX TNO VLCD BP0 BP1 BP2 BP3 PJ0/FP0 PJ1/FP1 PJ2/FP2 PJ3/FP3 PJ4/FP4 PJ5/FP5 PJ6/FP6 PJ7/FP7 PI0/FP8 PI1/FP9 PI2/FP10 PI3/FP11 PI4/FP12 17 Figure 17-1 100-pin QFP pinout for the MC68HC05F32 TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com MECHANICAL DATA MOTOROLA 17-1 Freescale Semiconductor, Inc. 17.2 100-pin QFP mechanical dimensions 4X 0.20 (0.008) H L-M N 4X 25 TIPS 100 76 0.20 (0.008) T L-M N 1 75 Freescale Semiconductor, Inc... -L- -M- BV NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -L-, -M- AND -N- TO BE DETERMINED AT DATUM -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -T-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.100) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.350 (0.014). MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.070 (0.003). 3X VIEW Y B1 V1 DIM A A1 B B1 C C1 C2 D E F G J K R1 S S1 U V V1 W Z 1 2 3 25 51 26 A1 -N- 50 S1 A S C -H- -T- SEATING PLANE 2X 02 0.08 (0.003) T MILLIMETERS MIN MAX 14.00 BSC 7.00 BSC 14.00 BSC 7.00 BSC 1.60 0.05 0.15 1.35 1.45 0.17 0.27 0.45 0.75 0.17 0.23 0.50 BSC 0.09 0.20 0.50 REF 0.10 0.20 16.00 BSC 8.00 BSC 0.09 0.16 16.00 BSC 8.00 BSC 0.20 REF 1.00 REF 0_ 7_ 0_ 12 _ 5_ 13 _ INCHES MIN MAX 0.551 BSC 0.276 BSC 0.551 BSC 0.276 BSC 0.063 0.002 0.006 0.053 0.057 0.007 0.011 0.018 0.030 0.007 0.009 0.20 BSC 0.004 0.008 0.020 REF 0.004 0.008 0.630 BSC 0.315 BSC 0.004 0.006 0.630 BSC 0.315 BSC 0.008 REF 0.039 REF 0_ 7_ 0_ 12 _ 5_ 13 _ 2X 03 VIEW AA S 0.05 (0.002) BASE METAL W 1 2XR F R1 C L G C2 0.25 (0.010) GAGE PLANE PLATING J D U C1 Z VIEW AA K E AB -X- X=L, M, N 0.08 (0.003) M T L-M S N S AB SECTION AB-AB ROTATED 90 CLOCKWISE VIEW Y CASE 983-01 17 Figure 17-2 100-pin QFP mechanical dimensions TPG MOTOROLA 17-2 For More Information On This Product, Go to: www.freescale.com MECHANICAL DATA MC68HC05F32 Freescale Semiconductor, Inc. 17.3 80-pin QFP pinout for the MC68HC05F32 Freescale Semiconductor, Inc... 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 PA6 PA5 PA4 PA3 PA2 PA1 PA0 OSC1 OSC2 IRQ VSS VDD RESET PB7 PB6 PB5 PB4 PB3 PB2 PB1 PA7 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PE0/TCAP1 PE1/TCMP1 PE2/TCAP2 PE3/TCMP2 PE4 PE5/PWM1 PE6/PWM2 PE7/PWM3 PC0/TCAP3 PC4 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PB0 PG7/FP31 PG6/FP30 PG5/FP29 PG4/FP28 PG3/FP27 PG2/FP26 PG1/FP25 PG0/FP24 PF7/FP23 PF6/FP22 PF5/FP21 PF4/FP20 PF3/FP19 PF2/FP18 PF1/FP17 PF0/FP16 PI7/FP15 PI6/FP14 PI5/FP13 Figure 17-3 80-pin QFP pinout for the MC68HC05F32 Note: The 80-pin version is only a bond option. Pins PE4, PD7-PD0, PC4, PC5 are shared with module functions which cannot work on the 80-pin package. These modules and their corresponding pin functions should not be enabled. PC5 TNX TNO BP0 BP1 BP2 BP3 PJ0/FP0 PJ1/FP1 PJ2/FP2 PJ3/FP3 PJ4/FP4 PJ5/FP5 PJ6/FP6 PJ7/FP7 PI0/FP8 PI1/FP9 PI2/FP10 PI3/FP11 PI4/FP12 17 TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com MECHANICAL DATA MOTOROLA 17-3 Freescale Semiconductor, Inc. 17.4 80-pin QFP mechanical dimensions L B 41 40 0.20 M C A - B S D S 0.05 A - B 0.20 M H A - B S D S B P Case No. 841B - 01 80 QFP 60 61 - A, B, D Detail "A" F Freescale Semiconductor, Inc... -AL -BB V Detail "A" 80 1 A 0.20 M C A - B S D S 0.05 A - B S 0.20 M H A - B S D S -D20 21 J N D Section B-B 0.20 M C A - B S D S Base metal U Detail "C" M T R Q C -CSeating plane E H G Datum -H- plane M K W X Detail "C" 17 Dim. A B C D E F G H J K L Min. Max. 13.90 14.10 13.90 14.10 2.15 2.45 0.22 0.38 2.00 2.40 0.22 0.33 0.65 BSC -- 0.250 0.130 0.230 0.65 0.95 12.35 REF Notes 1. Datum plane -H- is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 2. Datums A-B and -D to be determined at datum plane -H-. 3. Dimensions S and V to be determined at seating plane -C-. 4. Dimensions A and B do not include mould protrusion. Allowable mould protrusion is 0.25mm per side. Dimensions A and B do include mould mismatch and are determined at datum plane -H-. 5. Dimension D does not include dambar protrusion. Allowable dambar protrusion shall be 0.08 total in excess of the D dimension at maximum material condition. Dambar cannot be located on the lower radius or the foot. 6. Dimensions and tolerancing per ANSI Y 14.5M, 1982. 7. All dimensions in mm. Dim. M N Q R S T U V W X Min. Max. 5 10 0.130 0.170 0 7 0.13 0.30 16.95 17.45 0.13 -- 0 -- 16.95 17.45 0.35 0.45 1.6 REF Figure 17-4 80-pin QFP mechanical dimensions TPG MOTOROLA 17-4 For More Information On This Product, Go to: www.freescale.com MECHANICAL DATA MC68HC05F32 Freescale Semiconductor, Inc. 18 ORDERING INFORMATION This section describes the information needed to order the MC68HC05F32. To initiate a ROM pattern for the MCU, it is necessary to first contact your local field service office, local sales person or Motorola representative. Please note that you will need to supply details such as: mask option selections; temperature range; oscillator frequency; package type; electrical test requirements; and device marking details so that an order can be processed, and a customer specific part number allocated. Refer to Table 18-1 for appropriate part numbers. Freescale Semiconductor, Inc... Table 18-1 MC order numbers Device title MC68HC05F32 MC68HC705F32 MC68HC05F32 MC68HC705F32 Package type 100-pin QFP 80-pin QFP 100-pin QFP 80-pin QFP 100-pin QFP 80-pin QFP 100-pin QFP 80-pin QFP Temperature 0 to 70 C 0 to 70 C -40 to 85 C -40 to 85 C Part number MC68HC05F32PU MC68HC05F32FU MC68HC705F32PU MC68HC705F32FU MC68HC05F32CPU MC68HC05F32CFU MC68HC705F32CPU MC68HC705F32CFU 18 TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com ORDERING INFORMATION MOTOROLA 18-1 Freescale Semiconductor, Inc. 18.1 EPROMs For the MC68HC05F32, a 64K byte EPROM programmed with the customer's software (positive logic for address and data) should be submitted for pattern generation. All unused bytes should be programmed to $00. The EPROM should be clearly labelled, placed in a conductive IC carrier and securely packed. Freescale Semiconductor, Inc... 18.2 Verification media All original pattern media (EPROMs) are filed for contractual purposes and are not returned. A computer listing of the ROM code will be generated and returned with a listing verification form. The listing should be thoroughly checked and the verification form completed, signed and returned to Motorola. The signed verification form constitutes the contractual agreement for creation of the custom mask. If desired, Motorola will program blank EPROMs (supplied by the customer) from the data file used to create the custom mask, to aid in the verification process. 18.3 ROM verification units(RVU) Ten MCUs containing the customer's ROM pattern will be provided for program verification. These units will have been made using the custom mask but are for ROM verification only. For expediency, they are usually unmarked and are tested only at room temperature (25C) and at 5 Volts. These RVUs are included in the mask charge and are not production parts. They are neither backed nor guaranteed by Motorola Quality Assurance. 18 TPG MOTOROLA 18-2 For More Information On This Product, Go to: www.freescale.com ORDERING INFORMATION MC68HC05F32 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... The MC68HC705F32 is a device very similar to the MC68HC05F32 but has 32256 bytes of user EPROM with 496 bytes of bootloader ROM. It does have the same amount of RAM, LCD RAM, EEPROM, I/O, and user vectors. It also has the same on-board peripherals as the MC68HC05F32. There is also an 80-pin version of the MC68HC705F32, this has a reduced I/O count and reduced functionality. It has no 32 kHz clock system, SPI, SCI or A/D converter. The timer has three input captures (no TCAP4) and the LCD driver only has 32 frontplanes. A ry na MC68HC705F32 i lim re P ata d Note: The 80-pin version is only a bond option. Pins PE4, PD7-PD0, PC4, PC5 are shared with module functions which cannot work on the 80-pin package. These modules and their corresponding pin functions should not be enabled. A.1 * * Features 32256 bytes of user EPROM plus 16 bytes of user vectors 496 bytes of bootloader ROM P li re in m yd ar ta a P MC68HC05F32 li re in m yd ar ta a TPG For More Information On This Product, Go to: www.freescale.com MC68HC705F32 MOTOROLA A-1 A Freescale Semiconductor, Inc. PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 OSC1 OSC2 OSC3 OSC4 Keyboard interrupt 32256 bytes user EPROM 496 bytes bootloader ROM 16 bytes for vectors PWM Freescale Semiconductor, Inc... Pr 2 2 lim e 920 bytes RAM 20 bytes LCD RAM 256 bytes user EEPROM Port B SCI SPI 3 Port C2 ar in REFRESH Timer yd 3 Port A OC2 IC2 OC1 IC1 IC3 IC4 TDO RDI MISO MOSI SCK SS Port E ta a PWM3 PWM2 PWM1 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 AVDD VRH VRL/AVSS PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 TNO TNX Oscillator and divider 32 kHz independent clock system, oscillator and divider3 Core timer Periodic interrupt COP watchdog AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 VDD VSS IRQ/VPP RESET VLCD BP3 BP2 BP1 BP0 M68HC05 CPU Port H1, 2 PI7 PI6 PI5 PI4 PI3 PI2 PI1 PI0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 1. When not being used to output the LCD frontplanes, port G and port F are input only, while port H, port I and port J are output only. 2. In the 80-pin package there is no port H and only pins PC0, PC4 and PC5 are available on port C. 3. These modules are not available in the 80-pin package. 4. In the 80-pin package there are only 32 frontplanes. Figure A-1 MC68HC705F32 block diagram P A MOTOROLA A-2 lim re yd ar in ta a PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 P lim re Port G1 yd ar in LCD driver4 FP23 FP22 FP21 FP20 FP19 FP18 FP17 FP16 DTMF/ melody generator FP39 FP38 FP37 FP36 FP35 FP34 FP33 FP32 FP31 FP30 FP29 FP28 FP27 FP26 FP25 FP24 FP15 FP14 FP13 FP12 FP11 FP10 FP9 FP8 Port F1 Port I1 FP7 FP6 FP5 FP4 FP3 FP2 FP1 FP0 Port J1 Port D 8-channel A/D converter3 ta a TPG For More Information On This Product, Go to: www.freescale.com MC68HC705F32 MC68HC05F32 Freescale Semiconductor, Inc. A.2 A.2.1 Pin descriptions IRQ/VPP As for the MC68HC05F32, this is an input-only pin for external interrupt sources. It also serves as the EPROM programming voltage input pin (VPP) on the MC68HC705F32. Freescale Semiconductor, Inc... A.3 Memory and registers The MC68HC705F32 has a 64K byte memory map consisting of registers (for I/O, control and status), user RAM, user ROM, EEPROM, bootloader ROM and reset and interrupt vectors as shown in Figure A-2. P lim re ry na i ata d A.3.1 Registers All the I/O, control and status registers of the MC68HC705F32 are contained within the first 80 byte block of the memory map, as detailed in Table A-1. P li re in m yd ar ta a P MC68HC05F32 li re in m yd ar ta a TPG For More Information On This Product, Go to: www.freescale.com MC68HC705F32 MOTOROLA A-3 A Freescale Semiconductor, Inc. MC68HC705F32 $0000 I/O (80 bytes) $0050 Unused $0054 $0068 RAM (920 bytes) LCD RAM (20 bytes) $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $1A $1B $1C $1D $1E Port A data (PORTA) Port B data (PORTB) Port C data (PORTC) Port D data (PORTD) Port A DDR (DDRA) Port B DDR (DDRB) Port C DDR (DDRC) Port D DDR (DDRD) Ctimer control/status (CTCSR) Ctimer counter (CTCR) Port E data (PORTE) Port E DDR (DDRE) Port E control (PECR) Row freq. control (FCR) Column freq. control (FCC) Tone control (TNCR) Port F data (PORTF) Port F control (PFCR) Port G data (PORTG) Port G control (PGCR) Port H data (PORTH) (1) Port H control (PHCR)(1) Port I data (PORTI) Port I control (PICR) Port J data (PORTJ) Port J control (PJCR) Port D control (PDCR) Key control (KCR) EEPROM prog. (EEPROG) EPROM prog. (PROG) LCD control (LCD) Freescale Semiconductor, Inc... Stack $0400 EEPROM (256 bytes) $0500 Unused $8000 Pr lim e yd ar in $28 $29 $2A $2B $2C $2D $2E ta a Counter 1 high (CNTH/1) Counter 1 low (CNTL/1) Alt. counter high 1 (ACNTH/1) Alt. counter low 1 (ACNTL/1) Timer 1 control 1 (TCR1/1) Timer 1 control 2 (TCR2/1) Timer 1 status (TSR/1) User EPROM (32256 bytes) $FF00 P Bootloader ROM (496 bytes) User vectors (16 bytes) lim re $20 $21 $22 $23 $24 $25 $26 $27 yd ar in $30 $31 $32 $33 $34 $35 $36 $37 $38 $39 $3A $3B $3C $3D $3E ta a Capture 3 high (ICR3H) Capture 3 low (ICR3L) Compare 3 high (OCR3H) Compare 3 low (OCR3L) Capture 4 high (ICR4H) Capture 4 low (ICR4L) Compare 4 high (OCR4H) Compare 4 low (OCR4L) Counter 2 high (CNTH/2) Counter 2 low (CNTL/2) Alt. counter high 2 (ACNTH/2) Alt. counter low 2 (ACNTL/2) Timer 2 control 1 (TCR1/2)(1) Timer 2 control 2 (TCR2/2)(1) Timer 2 status (TSR/2)(1) PWM control (PWMCR) PWM data 1 (PWMD1) PWM data 2 (PWMD2) PWM data 3 (PWMD3) SPI control (SPCR) (1) SPI status (SPSR) (1) SPI data I/O (SPDAT) (1) SCI data (SCDAT) (1) SCI control 1 (SCCR1) (1) SCI control 2 (SCCR2) (1) SCI status (SCSR) (1) SCI baud rate (BAUD) (1) CPI control/status (CPICSR) System options (SOR) A/D data (ADDATA) (1) A/D status/control (ADSCR) (1) $FFF0 $FFFF Capture 1 high (ICR1H) Capture 1 low (ICR1L) Compare 1 high (OCR1H) Compare 1 low (OCR1L) Capture 2 high (ICR2H) Capture 2 low (ICR2L) Compare 2 high (OCR2H) Compare 2 low (OCR2L) P A MOTOROLA A-4 lim re (1) Not applicable to 80-pin package. yd ar in $40 $41 $42 $43 $44 $45 $46 $47 $48 $49 $4A $4B $4C $4D $4E $4F ta a Figure A-2 Memory map of the MC68HC705F32 TPG For More Information On This Product, Go to: www.freescale.com MC68HC705F32 MC68HC05F32 Freescale Semiconductor, Inc. Table A-1 Register outline Register Name Port A data (PORTA) Key interrupt status (KISR) Port B data (PORTB) Port C data (PORTC) Port D data (PORTD) Port A data direction (DDRA) Port B data direction (DDRB) Address bit 7 $0000 $0000 $0001 $0002 $0003 PB7 PC7 PD7 PA7 bit 6 PA6 bit 5 PA5 bit 4 PA4 PA3 Freescale Semiconductor, Inc... Port C data direction (DDRC) Port D data direction ((DDRD) Pr lim e $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F $0010 $0011 0 0 MS1 PE7 TOF ry na i PB6 PB5 PB4 PC6 PD6 PC5 PD5 PC4 PD4 RTIF TOFE RTIE PE6 PE5 PE4 PB3 PC3 PD3 ata d bit 3 bit 2 PA2 PB2 PC2 PD2 bit 1 bit 0 PA0 State on reset undefined 0000 0000 PA1 PB1 PB0 PC0 PD0 undefined undefined undefined 0000 0000 0000 0000 0000 0000 0000 0000 PC1 PD1 Core timer control/status (CTCSR) Core timer counter (CTCR) Port E data (PORTE) Port E data direction (DDRE) Port E control (PECR) DTMF row freq. control (FCR) DTMF column freq. control (FCC) DTMF tone control (TNCR) Port F data (PORTF) Port F control (PFCR) Port G data (PORTG) RTOF RRTIF RT1 RT0 0000 0011 0000 0000 PE3 0 0 MS0 PF7 Port G control (PGCR) Port H data (PORTH) Port H control (PHCR) Port I data (PORTI) Port I control (PICR) Port J data (PORTJ) Port J control (PJCR) Port D control (PDCR) Key control (KCR) Pr $0012 li e $0013 $0015 $0016 $0017 $0018 $0019 PG7 in m PF6 PG6 PH6 PI7 PI6 PJ6 TGER TGEC TNOE PF5 PF4 PF3 yd ar 0 0 PG4 PG3 PH4 PH3 PI5 PI4 PI3 FCR4 FCR3 FCR2 FCR1 FCR0 undefined ta a 0 0 PF2 0 PF1 PG2 PG1 PH2 PH1 PE2 PE1 PE0 undefined 0000 0000 0 0000 0000 FCC4 FCC3 FCC2 FCC1 FCC0 undefined 0 PF0 0000 0000 undefined 0000 0000 PG0 undefined 0000 0000 PG5 $0014 PH7 PH5 PH0 0000 0000 0000 0000 PI2 PI1 PI0 0000 0000 0000 0000 PJ7 PJ5 PJ4 PJ3 $001A $001B $001C KF 0 KIE CPEN 0 EDG5 EDG4 EDG3 EDG2 EDG1 EDG0 0000 0000 0 ER1 ER0 LATCH EERC EEPGM 0000 0000 TS0 ELATCH 0 EPGM 0000 0000 EEPROM prog. (EEPROG) EPROM prog. (PROG) LCD control (LCD) Capture 1 high (ICR1H) Capture 1 low (ICR1L) P li re $0020 $0021 $001D $001E WTLCDO FSEL1 FSEL0 I NTVLCD FDISP MUX4 MUX3 EXTVON 0000 0000 in m 0 yd ar 0 TS1 ta a PJ2 PJ1 PJ0 0000 0000 0000 0000 0000 0000 (bit 15) (bit 8) undefined undefined TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com MC68HC705F32 MOTOROLA A-5 A Freescale Semiconductor, Inc. Table A-1 Register outline Register Name Compare 1 high (OCR1H) Compare 1 low (OCR1L) Capture 2 high (ICR2H) Capture 2 low (ICR2L) Compare 2 high (OCR2H) Compare 2 low (OCR2L) Counter 1 high (CNTH/1) Counter 1 low (CNTL/1) Address bit 7 $0022 $0023 $0024 $0025 (bit 15) (bit 15) bit 6 bit 5 bit 4 bit 3 Freescale Semiconductor, Inc... Alternate counter 1 high (ACNTH/1) Alternate counter 1 low (ACNTL/1) Timer1 control 1 (TCR1/1) Timer1 control 2 (TCR2/1) Timer1 status (TSR/1) P lim re $0027 $0028 (bit 15) $0029 $002A (bit 15) $002B $002C $002D $002E ICI1E 0 IC1F $0030 $0031 $0032 $0033 (bit 15) (bit 15) $0026 (bit 15) yd ar in 0 OCI2E OC1F 0 CO2E ta a bit 2 bit 1 bit 0 (bit 8) State on reset undefined undefined (bit 8) undefined undefined (bit 8) undefind undefined (bit 8) 1111 1111 1111 1100 (bit 8) 1111 1111 1111 1100 ICI2E OCI1E TOIE CO1E IEDG1 IEDG2 OLVL1 0000 0uu0 IC2F TOF TCAP1 TCAP2 OC2F Capture 3 high (ICR3H) Capture 3 low (ICR3L) Compare 3 high (OCR3H) Compare 3 low (OCR3L) Capture 4 high (ICR4H) Capture 4 low (ICR4L) Compare 4 high (OCR4H) Compare 4 low (OCR4L) Counter 1 high (CNTH/1) Counter 1 low (CNTL/1) Pr $0036 lim e $0034 (bit 15) $0035 (bit 15) (bit 15) $003B ICI3E 0 IC3F ar in yd ta a 0 0 OLVL2 0000 0000 0 uuuu uuu0 (bit 8) undefined undefined (bit 8) undefined undefined undefined undefined undefined undefined $0037 $0038 $0039 $003A (bit 15) (bit 8) 1111 1111 1111 1100 Alternate counter 2 high (ACNTH/1) Alternate counter 2 low (ACNTL/1) Timer2 control 1 (TCR1/2) Timer2 control 2 (TCR2/2) Timer2 status (TSR/2) $003C $003D $003E ICI4E OCI3E TOIE CO3E IEDG3 IEDG4 IC4F PWM control (PWMCR) PWM data 1 (PWMD1) PWM data 2 (PWMD2) PWM data 3 (PWMD3) SPI control (SPCR) $0040 $0041 $0042 $0043 Pr lim e $0044 SPIE ar in OC3F 0 OCI4E TOF TCAP3 TCAP4 OC4F yd 0 CO4E ta a 0 0 RA1 (bit 8) 1111 1111 1111 1100 0000 0uu0 0000 0000 0 uuuu uuu0 POL3 POL2 POL1 RA0 0001 1100 1000 0000 1000 0000 1000 0000 SPE DOD MSTR CPOL CPHA SPR1 SPR0 0000 01uu A TPG MOTOROLA A-6 For More Information On This Product, Go to: www.freescale.com MC68HC705F32 MC68HC05F32 Freescale Semiconductor, Inc. Table A-1 Register outline Register Name SPI status (SPSR) SPI data I/O (SPDAT) SCI data (SCDAT) SCI control 1 (SCCR1) SCI control 2 (SCCR2) SCI status (SCSR) SCI baud rate (BAUD) Address bit 7 $0045 $0046 $0047 $0048 $0049 R8 TIE bit 6 bit 5 0 bit 4 MODF SPIF WCOL Freescale Semiconductor, Inc... CPI control status (CPICSR) System options (SOR) A/D data (ADDATA) A/D status/control (ADSCR) P lim re $004A TDRE TCLR 0 $004B $004C $004D LVIF $004E ry na i T8 0 M TCIE TC 0 CPIF LVIE RIE ILIE RDRF IDLE 0 LVION CPIE SC 0 ata d bit 3 0 bit 2 0 0 WAKE TE OR 0 RE NF 0 FE 0 IRQ 0 bit 1 bit 0 0 State on reset 0000 0000 undefined undefined 0 SBK 0 uu00 0000 0000 0000 1100 0000 RWU SCP1 SCP0 RCKB SCR2 SCR1 SCR0 0000 0uuu RFQ1 RFQ0 0000 0000 KEYMUX KEYCLRPUEN 0000 0000 undefined CH3 CH2 CH1 CH0 0000 0000 u = undefined $004F COCO ADRC ADON P li re in m yd ar ta a P MC68HC05F32 li re in m yd ar ta a TPG For More Information On This Product, Go to: www.freescale.com MC68HC705F32 MOTOROLA A-7 A Freescale Semiconductor, Inc. A.3.2 EPROM The MC68HC705F32 has 32256 bytes of EPROM located from $8000 to $FDFF, plus 16 bytes of user vectors from $FFF0 to $FFFF. Up to 16 bytes of EPROM can be programmed simultaneously by correctly manipulating the bits in the EPROM programming register. A.3.2.1 EPROM programming register (PROG) Freescale Semiconductor, Inc... EPROM programming (PROG) EPGM -- EPROM program control 1 (set) - P lim re Address bit 7 $001D 0 yd ar in bit 6 bit 5 bit 4 bit 3 0 0 0 0 ta a bit 2 ELATCH bit 1 0 bit 0 State on reset EPGM 0000 0000 Programming power connected to the EPROM array. Programming power disconnected from the EPROM array. 0 (clear) - ELATCH and EPGM cannot be set on the same write operation. EPGM can only be set if ELATCH is set. EPGM is automatically cleared when ELATCH is cleared. ELATCH -- EPROM latch control 1 (set) - EPROM address and data buses configured for programming. EPROM address and data buses configured for normal reads 0 (clear) - ELATCH causes address and data buses to be latched when a write to EPROM is carried out. The EPROM cannot be read if ELATCH = 1. This bit should not be set unless a programming voltage is applied to the VPP pin. P lim re yd ar in ta a A.3.2.2 EPROM programming operation The following steps should be taken to program a byte of EPROM: 1) Apply the programming voltage VPP to the IRQ pin. 2) Set the ELATCH bit. 3) Write to the EPROM address. 5) Clear the ELATCH bit. 4) Set the EPGM bit for a time tEPGM to apply the programming voltage. If the address bytes A15-A4 do not change, i.e. all bytes are located within the same 16 byte address block, then multibyte programming is permitted. The multibyte programming facility allows up to 16 bytes of data to be written to the desired addresses after the ELATCH bit has been set. P lim re yd ar in ta a A TPG MOTOROLA A-8 For More Information On This Product, Go to: www.freescale.com MC68HC705F32 MC68HC05F32 Freescale Semiconductor, Inc. A.4 Electrical specifications This section gives the electrical specifications for the MC68HC705F32, the EPROM version of the MC68HC05F32. Contained in this section is the information specific to the MC68HC705F32 which differs from that detailed in Section 16. A.4.1 EPROM characteristics Freescale Semiconductor, Inc... Characteristic EPROM programming voltage rate EPROM programming voltage EPROM programming time P lim re ry na i Symbol V PP V PP t EPGM ata d Table A-2 EPROM characteristics Value V SS - 0.3 to +17 + 0.5 typ. 17.0 min. 4.0 Unit V V ms A.4.2 DC levels for low voltage reset and LVI Table A-3 DC levels for low voltage reset and LVI (TA = 0C to 60C, unless otherwise stated) Characteristic Symbol Min. Power-on reset voltage V RON 2.55 Power-off reset voltage VROFF 2.45 Low voltage interrupt VLVI 2.75 P li re in m yd ar Typ. 2.8 2.7 3.0 ta a Unit V V V Max. 3.05 2.95 3.25 P MC68HC05F32 li re in m yd ar ta a TPG For More Information On This Product, Go to: www.freescale.com MC68HC705F32 MOTOROLA A-9 A Freescale Semiconductor, Inc. A.5 A.5.1 Mechanical data 100-pin QFP pinout for the MC68HC705F32 Freescale Semiconductor, Inc... AVDD PD0/AN0 PD1/AN1 PD2/AN2 PD3/AN3 PD4/AN4 PD5/AN5 PD6/AN6 PD7/AN7 AVSS PE0/TCAP1 PE1/TCMP1 PE2/TCAP2 PE3/TCMP2 PE4/REFRESH PE5/PWM1 PE6/PWM2 PE7/PWM3 PC0/TCAP3 PC1/TCAP4 PC2/RDI PC3/TDO PC4/MISO VDD VSS P 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 lim re yd ar in ta a 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PH1/FP33 PH0/FP32 PG7/FP31 PG6/FP30 PG5/FP29 PG4/FP28 PG3/FP27 PG2/FP26 PG1/FP25 PG0/FP24 PH5/FP37 PH4/FP36 PH3/FP35 PH2/FP34 PF7/FP23 PF6/FP22 PF5/FP21 PF4/FP20 PF3/FP19 PF2/FP18 PF1/FP17 PF0/FP16 PI7/FP15 PI6/FP14 PI5/FP13 Figure 18-1 100-pin QFP pinout for the MC68HC705F32 For package dimensions, refer to Section 17.2. P A MOTOROLA A-10 lim re PC5/MOSI PC6/SCK PC7/SS OSC3 OSC4 TNX TNO VLCD BP0 BP1 BP2 BP3 PJ0/FP0 PJ1/FP1 PJ2/FP2 PJ3/FP3 PJ4/FP4 PJ5/FP5 PJ6/FP6 PJ7/FP7 PI0/FP8 PI1/FP9 PI2/FP10 PI3/FP11 PI4/FP12 P lim re 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VRH PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 OSC1 OSC2 IRQ/VPP VSS VDD RESET PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PH7/FP39 PH6/FP38 yd ar in ta a yd ar in ta a For More Information On This Product, Go to: www.freescale.com MC68HC705F32 MC68HC05F32 Freescale Semiconductor, Inc. A.5.2 80-pin QFP pinout for the MC68HC705F32 Freescale Semiconductor, Inc... P Note: li re Figure 18-2 80-pin QFP pinout for the MC68HC705F32 PC5 TNX TNO BP0 BP1 BP2 BP3 PJ0/FP0 PJ1/FP1 PJ2/FP2 PJ3/FP3 PJ4/FP4 PJ5/FP5 PJ6/FP6 PJ7/FP7 PI0/FP8 PI1/FP9 PI2/FP10 PI3/FP11 PI4/FP12 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 PA7 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PE0/TCAP1 PE1/TCMP1 PE2/TCAP2 PE3/TCMP2 PE4 PE5/PWM1 PE6/PWM2 PE7/PWM3 PC0/TCAP3 PC4 VDD P 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 lim re ry na i 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 PA6 PA5 PA4 PA3 PA2 PA1 PA0 OSC1 OSC2 IRQ/VPP VSS VDD RESET PB7 PB6 PB5 PB4 PB3 PB2 PB1 ata d PB0 PG7/FP31 PG6/FP30 PG5/FP29 PG4/FP28 PG3/FP27 PG2/FP26 PG1/FP25 PG0/FP24 PF7/FP23 PF6/FP22 PF5/FP21 PF4/FP20 PF3/FP19 PF2/FP18 PF1/FP17 PF0/FP16 PI7/FP15 PI6/FP14 PI5/FP13 in m yd ar ta a The 80-pin version is only a bond option. Pins PE4, PD7-PD0, PC4, PC5 are shared with module functions which cannot work on the 80-pin package. These modules and their corresponding pin functions should not be enabled. For package dimensions, refer to Section 17.4. P MC68HC05F32 li re in m yd ar ta a For More Information On This Product, Go to: www.freescale.com MC68HC705F32 MOTOROLA A-11 A Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... P lim re yd ar in ta a THIS PAGE LEFT BLANK INTENTIONALLY P lim re yd ar in ta a P A MOTOROLA A-12 lim re yd ar in ta a For More Information On This Product, Go to: www.freescale.com MC68HC705F32 MC68HC05F32 Freescale Semiconductor, Inc. GLOSSARY This section contains abbreviations and specialist words used in this data sheet and throughout the industry. Further information on many of the terms may be gleaned from Motorola's M68HC11 Reference Manual, M68HC11RM/AD, or from a variety of standard electronics text books. Freescale Semiconductor, Inc... $xxxx %xxxx A/D, ADC Bootstrap mode Byte CCR CERQUAD Clear CMOS COP CPU D/A, DAC EEPROM EPROM The digits following the `$' are in hexadecimal format. The digits following the `%' are in binary format. Analog-to-digital (converter). In this mode the device automatically loads its internal memory from an external source on reset and then allows this program to be executed. Eight bits. Condition codes register; an integral part of the CPU. A ceramic package type, principally used for EPROM and high temperature devices. `0' -- the logic zero state; the opposite of `set'. Complementary metal oxide semiconductor. A semiconductor technology chosen for its low power consumption and good noise immunity. Computer operating properly. aka `watchdog'. This circuit is used to detect device runaway and provide a means for restoring correct operation. Central processing unit. Digital-to-analog (converter). Electrically erasable programmable read only memory. aka `EEROM'. Erasable programmable read only memory. This type of memory requires exposure to ultra-violet wavelengths in order to erase previous data. aka `PROM'. Electrostatic discharge. In this mode the internal address and data bus lines are connected to external pins. This enables the device to be used in much more complex systems, where there is a need for external memory for example. ESD Expanded mode TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com GLOSSARY MOTOROLA xiii Freescale Semiconductor, Inc. EVS HCMOS I/O Input capture Evaluation system. One of the range of platforms provided by Motorola for evaluation and emulation of their devices. High-density complementary metal oxide semiconductor. A semiconductor technology chosen for its low power consumption and good noise immunity. Input/output; used to describe a bidirectional pin or function. (IC) This is a function provided by the timing system, whereby an external event is `captured' by storing the value of a counter at the instant the event is detected. This refers to an asynchronous external event and the handling of it by the MCU. The external event is detected by the MCU and causes a predetermined action to occur. Interrupt request. The overline indicates that this is an active-low signal format. A kilo-byte (of memory); 1024 bytes. Liquid crystal display. Least significant byte. Motorola's family of 8-bit MCUs. Microcontroller unit. Motorola interconnect bus. A single wire, medium speed serial communications protocol. Most significant byte. Half a byte; four bits. Non-return to zero. The opcode is a byte which identifies the particular instruction and operating mode to the CPU. See also: prebyte, operand. The operand is a byte containing information the CPU needs to execute a particular instruction. There may be from 0 to 3 operands associated with an opcode. See also: opcode, prebyte. (OC) This is a function provided by the timing system, whereby an external event is generated when an internal counter value matches a predefined value. Plastic leaded chip carrier package. Phase-locked loop circuit. This provides a method of frequency multiplication, to enable the use of a low frequency crystal in a high frequency circuit. This byte is sometimes required to qualify an opcode, in order to fully specify a particular instruction. See also: opcode, operand. Freescale Semiconductor, Inc... Interrupt IRQ K byte LCD LSB M68HC05 MCU MI BUS MSB Nibble NRZ Opcode Operand Output compare PLCC PLL Prebyte TPG MOTOROLA xiv For More Information On This Product, Go to: www.freescale.com GLOSSARY MC68HC05F32 Freescale Semiconductor, Inc. Pull-down, pull-up These terms refer to resistors, sometimes internal to the device, which are permanently connected to either ground or VDD. PWM Pulse width modulation. This term is used to describe a technique where the width of the high and low periods of a waveform is varied, usually to enable a representation of an analog value. Quad flat pack package. Random access memory. Fast read and write, but contents are lost when the power is removed. Radio frequency interference. Real-time interrupt. Read-only memory. This type of memory is programmed during device manufacture and cannot subsequently be altered. A standard serial communications protocol. Successive approximation register. Serial communications interface. `1' -- the logic one state; the opposite of `clear'. An area in the central belt of Scotland, so called because of the concentration of semiconductor manufacturers and users found there. In this mode the device functions as a self contained unit, requiring only I/O devices to complete a system. Serial peripheral interface. This mode is intended for factory testing. Transistor-transistor logic. Universal asynchronous receiver transmitter. Voltage controlled oscillator. QFP RAM RFI RTI ROM RS-232C SAR SCI Set Silicon glen Single chip mode SPI Test mode TTL UART VCO Watchdog Wired-OR Word XIRQ Freescale Semiconductor, Inc... see `COP'. A means of connecting outputs together such that the resulting composite output state is the logical OR of the state of the individual outputs. Two bytes; 16 bits. Non-maskable interrupt request. The overline indicates that this has an active-low signal format. TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com GLOSSARY MOTOROLA xv Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA xvi For More Information On This Product, Go to: www.freescale.com GLOSSARY MC68HC05F32 Freescale Semiconductor, Inc. INDEX In this index numeric entries are placed first; page references in italics indicate that the reference is to a figure. 100-pin QFP MC68HC05F32 pinout 17-1 MC68HC705F32 pinout A-10 mechanical dimensions 17-2 32 kHz clock system during STOP mode 13-2 during WAIT mode 13-2 refresh clock 13-2 80-pin QFP MC68HC05F32 pinout 17-3 MC68HC705F32 pinout A-11 mechanical dimensions 17-4 Freescale Semiconductor, Inc... B BAUD -- baud rate register 11-14 SCP1, SCP0 - serial prescaler select bits 11-15 SCT2, SCT1, SCT0 - SCI rate select bits 11-15 baud rate selection 11-16 bit set/clear addressing mode 15-13 bit test and branch addressing mode 15-13 block diagrams A/D converter 9-2 core timer 5-1 LCD 8-1 MC68HC05F32 1-3 MC68HC705F32 A-2 programmable timer 6-2 PWM 12-1 SCI 11-2 SPI 10-5 BP3-PB0 2-7 A A - accumulator 15-1 A/D converter ADDATA 9-5 ADSCR 9-3 AN7-AN0 2-6 analog input 9-5 block diagram 9-2 channel selection 9-1, 9-4 conversion 9-3 during STOP mode 9-5 during WAIT mode 9-5 operation 9-1 RC oscillator 9-3 stabilization 9-4 successive approximation (SAR) 9-1 ADDATA -- A/D result data register 9-5 addressing modes 15-5-15-13 ADON bit in ADSCR 9-4 ADRC bit in ADSCR 9-3 ADSCR -- A/D status/control register ADON - A/D converter on bit 9-4 ADRC - A/D RC oscillator flag 9-3 CH2-CH0 - A/D channel selection bits 9-4 COCO - conversion complete flag 9-3 alternate counter register 6-3 AN7-AN0 2-6 AVDD 2-6 AVSS 2-6 C C-bit in CCR 15-3 CCR - condition code register 15-2 CH2-CH0 bits in ADSCR 9-4 clocks - see oscillator clock CO1E bit in TCR1 6-5 CO2E bit in TCR2 6-6 COCO bit in ADSCR 9-3 control timing 16-5 COP 14-2 COP watchdog timer 5-5 COP reset times 5-5 core timer block diagram 5-1 CTCR -- counter register 5-4 CTCSR -- control/status register 5-3 during STOP mode 5-5 during WAIT mode 5-5 interrupts 5-2, 14-4 counter alternate counter register 6-3 TPG MC68HC05F32 For More Information On This Product, Go to: www.freescale.com INDEX MOTOROLA xvii Freescale Semiconductor, Inc. counter register 6-3 programmable timer 6-1 CPEN-bit in EPROG 3-6 CPHA bit in SPCR 10-7 CPICSR CPIE - custom periodic interrupt enable 13-1 CPIF - custom periodic interrupt flag 13-1 RFQ1, RFQ0 - refresh frequency select 13-2 CPICSR -- custom periodic interrupt control/status register 13-1 CPIE bit in CPICSR 13-1 CPIF bit in CPICSR 13-1 CPOL 10-7 CPOL bit in SCCR1 11-11 CPOL bit in SPCR 10-7 CPU A - accumulator 15-1 addressing modes 15-5-15-13 CCR - condition code register 15-2 instruction set 15-3-15-11 PC - program counter 15-2 programming model 15-1 SP - stack pointer 15-2 stacking order 15-2 X - index register 15-2 crystal 2-8 CTCR -- core timer counter register 5-4 CTCSR -- core timer control/status register CTOF - core timer overflow 5-3 CTOFE- core timer overflow enable 5-3 RT1, RT0 real time interrupt rate select 5-4 RTIE - real time interrupt enable 5-3 RTIF - real time interrupt flag 5-3 erasing procedures 3-8 LATCH - latch bit 3-7 programming procedures 3-8 sample programming sequence 3-8 EERC-bit in EPROG 3-7 ELATCH bit in PROG A-8 electrical specifications A/D converter 16-9 control timing (5V) 16-5 DC characteristics (5V) 16-3 DTMF/melody generator 16-7 EPROM characteristics A-9 maximum ratings 16-1 PWM timing 16-8 thermal characteristics 16-2 EPGM bit in PROG A-8 EPROG - EEPROM programing register 3-6 EPROM multibyte programming A-8 PROG -- EPROM programming register A-8 programming A-8 ER1, ER0 bits in EPROG 3-7 extended addressing mode 15-12 external clock 2-8 EXTVON bit in LCD 8-10 Freescale Semiconductor, Inc... F FCC -- column frequency control register 7-4 FCR -- row frequency control register 7-4 FDISP bit in LCD 8-10 FE bit in SCSR 11-14 features MC68HC05F32 1-2 MC68HC705F32 A-1 flowcharts interrupt 14-5 STOP and WAIT 2-3 FP39-FP0 2-7 frontplane pins 2-7 D data retention mode 2-2 DC characteristics 16-3 direct addressing mode 15-7 DMG registers FCC -- column frequency control register 7-4 FCR -- row frequency control register 7-4 TNCR -- tone control register 7-4 DOD bit in SPCR 10-7 DTMF/melody generator (DMG) during STOP mode 7-8 during WAIT mode 7-8 features 7-1 operation 7-7 H H-bit in CCR 15-3 I I/O port structure 4-4 I/O ports I/O port structure 4-4 port A 4-2 port B 4-4 port C 4-5 port D 4-5 port E 4-6 ports F, G, H, I, J 4-6 E EDG0-EDG5 - trigger edge control 4-4 EEPGM-bit in EPROG 3-8 EEPROM 3-6 EPROG - EEPROM programing register 3-6 erase modes 3-7 MOTOROLA xviii For More Information On This Product, Go to: www.freescale.com INDEX MC68HC05F32 Freescale Semiconductor, Inc. programming 4-1 I-bit in CCR 15-3 IC1F, IC2F bits in TSR 6-7 IC1IE bit in TCR 6-5 IC2IE bit in TCR1 6-5 ICR1 -- input capture register 6-9 IDLE bit in SCSR 11-13 IEDG1 bit in TCR1 6-5 IEDG2 bit in TCR1 6-6 ILIE bit in SCCR2 11-11 illegal address reset 14-1 immediate addressing mode 15-6 indexed addressing modes 15-12 inherent addressing mode 15-6 input capture 6-9 instruction set 15-3-15-11 tables of instructions 15-5-15-11 interrupts 14-3 core timer 14-4 hardware 14-4 interrupt flowchart 14-5 keyboard 14-7 maskable 14-4 nonmaskable 14-4 priorities 14-4 programmable timer 14-6 real-time 5-2, 14-4 software (SWI) 14-4 INTVLCD bit in LCD 8-9 IRQ 2-5 IRQ bit in SOR 2-4 MUX4, MUX3 - multiplex ratio 8-10 WTLCDO - WAIT mode LCD only 8-9 low power modes 2-1 data retention 2-2 RESET, STOP, WAIT - as interrupt sequence 14-8 STOP 2-1 WAIT 2-2 LVIF, LVIE, LVION bits in SOR 2-4 Freescale Semiconductor, Inc... M M bit in SCCR1 11-10 mask options 1-2 maximum ratings 16-1 MC68HC05F32 block diagram 1-3 features 1-2 mask options 1-2 MC68HC705F32 block diagram A-2 features A-1 memory bootloader ROM 3-6 EEPROM 3-6 EPROM A-8 memory map 3-2, A-4 RAM 3-5 ROM 3-5 MISO 2-6 modes of operation low power modes 2-1 single-chip 2-1 MODF bit in SPSR 10-8 MOSI 2-6 MSTR 10-7 MSTR bit in SPCR 10-7 MUX4, MUX3 bits in LCD 8-10 K key control register EDG0-EDG5 - trigger edge control 4-4 KF - keyboard interrupt status flag 4-3 KIE - keyboard interrupt enable 4-4 keyboard interrupt 2-5, 4-2, 14-7 KEYCLR bit in SOR 2-4 KEYMUX bit in SOR 2-4 N N-bit in CCR 15-3 NF bit in SCSR 11-14 L LATCH-bit in EPROG 3-7 LCD block diagram 8-1 during STOP mode 8-10 during WAIT mode 8-10 RAM 8-2 timing diagrams 8-4-8-8 timing signals 8-4 voltage level selection 8-4 LCD -- LCD control register EXTVON - external LCD voltage ON/OFF 8-10 FDISP - display frequency 8-10 INTVLCD - internal voltage generator ON/OFF 8-9 O OC1IE bit in TCR1 6-5 OC2IE bit in TCR2 6-6 OCR1, OCR2 -- output compare registers 6-11 OLVL1 bit in TCR1 6-6 OLVL2 bit in TCR2 6-6 OR bit in SCSR 11-13 OSC1, OSC2 pins 2-7 OSC3, OSC4 pins 2-7 oscillator clock connections 2-9 crystal 2-8 MC68HC05F32 For More Information On This Product, Go to: www.freescale.com INDEX MOTOROLA xix Freescale Semiconductor, Inc. external clock 2-8 output compare 6-11 port B 4-4 port C 4-5 port D 4-5 port E 4-6 port registers data direction registers 4-7 port data registers 4-7 ports F, G, H, I, J 4-6 ports F, G, H, I, J pins 2-7 power-on reset 14-1 PROG -- EPROM programming register A-8 ELATCH - EPROM latch control A-8 EPGM - EPROM program control A-8 programmable timer block diagram 6-2 counter 6-1 during STOP mode 6-13 during WAIT mode 6-13 ICR1 6-9 interrupts 14-6 OCR1, OCR2 6-11 TCR1, TCR2 6-4 timing diagrams 6-13 TSR 6-7 programming EEPROM 3-8 EPROM A-8 PUEN bit in SOR 2-4 PWM 12-4 block diagram 12-1 control register 12-3 during reset 12-5 during STOP mode 12-5 during WAIT mode 12-4 waveforms 12-2, 12-3 PWM control register POL1 - PWM1 polarity 12-3 POL2 - PWM2 polarity 12-3 POL3 - PWM3 polarity 12-3 PWM timing 16-8 PWM1 2-6 PWM2 2-6 PWM3 2-6 P PA7-PA0 2-5 packages MC68HC05F32 100-pin QFP 17-1 MC68HC05F32 80-pin QFP 17-3 MC68HC705F32 100-pin QFP A-10 MC68HC705F32 80-pin QFP A-11 PB7-PB0 2-5 PC - program counter 15-2 PC7-PC0 2-6 PD7-PD0 2-6 PE7-PE0 2-6 pins AN7-AN0 2-6 AVDD 2-6 AVSS 2-6 BP3-BP0 2-7 FP39-FP0 2-7 IRQ 2-5 keyboard interrupt 2-5 MISO 2-6 MOSI 2-6 OSC1, OSC2 2-7 OSC3, OSC4 2-7 PA7-PA0 2-5 PB7-PB0 2-5 PC7-PC0 2-6 PD7-PD0 2-6 PE7-PE0 2-6 ports F, G, H, I, J 2-7 PWM1 2-6 PWM2 2-6 PWM3 2-6 RDI 2-6, 11-6 REFRESH 2-6 RESET 2-5, 14-1 SCK 2-6 SS 2-6 TCAP1 2-6 TCAP2 2-6 TCAP3 2-6 TCAP4 2-6 TCMP1 2-6 TCMP2 2-6 TDO 2-6 TNO, TNX 2-7 VDD, VSS 2-5 VLCD 2-7 VRH 2-6 POL1 bit in the PWM control register 12-3 POL2 bit in the PWM control register 12-3 POL3 bit in the PWM control register 12-3 POR - see power-on reset port A 4-2 keyboard interrupt 4-2 Freescale Semiconductor, Inc... R R8 bit in SCCR1 11-10 RC oscillator stabilization 9-3 RDI 2-6 RDI - receive data in 11-6 RDRF bit in SCSR 11-13 RE bit in SCCR2 11-12 real-time interrupts 5-2, 14-4 example RTI periods 5-4 receiver wake-up 11-5 REFRESH 2-6 register summary 3-3, A-5 relative addressing mode 15-13 MOTOROLA xx For More Information On This Product, Go to: www.freescale.com INDEX MC68HC05F32 Freescale Semiconductor, Inc. RESET 2-5 resets 14-1 COP 14-2 illegal address 14-1 power-on reset 14-1 RESET pin 2-5, 14-1 RFQ1, RFQ0 bits in CPICSR 13-2 RIE bit in SCCR2 11-11 RT1, RT0 bits in CTCSR 5-4 RTIE bit in CTCSR 5-3 RTIF bit in CTCSR 5-3 RWU bit in SCCR2 11-12 SPCR CPHA - clock phase 10-7 CPOL - clock polarity 10-7 DOD - direction of data 10-7 MSTR - master/slave mode select 10-7 SPE - SPI system enable 10-7 SPIE - SPI interrupt enable 10-6 SPR1, SPR0 - SPI clock select bits 10-7 SPI 10-9 block diagram 10-5 during STOP mode 10-9 during WAIT mode 10-9 features 10-1 rate selection 10-8 registers 10-6 SPI registers SPCR -- SPI control register 10-6 SPDAT -- SPI data I/O register 10-9 SPSR -- SPI status register 10-8 SPI signal descriptions master in slave out (MISO) 10-2 master out slave in (MOSI) 10-2 serial clock (SCK) 10-2 slave select (SS) 10-4 SPIE 10-6 SPSR MODF - SPI mode error interrupt status flag 10-8 SPIF - SPI interrupt request flag 10-8 WCOL - write collision 10-8 SS 2-6 STOP mode 2-1 successive approximation (SAR) - see A/D converter SWI - see interrupts system options register 2-4 Freescale Semiconductor, Inc... S SBK bit in SCCR2 11-12 SC bit in SOR 2-4 SCCR1 -- serial communications control register 1 11-9 CPOL - clock polarity bit 11-11 M - mode (select character format) 11-10 R8 - receive data bit 8 11-10 T8 - transmit data bit 8 11-10 WAKE - wake-up mode select bit 11-10 SCCR2 -- serial communications control register 2 11-11 ILIE - idle line interrupt enable 11-11 RE - receiver enable 11-12 RIE - receiver interrupt enable 11-11 RWU - receiver wake-up 11-12 SBK - send break 11-12 TCIE - transmit complete interrupt enable 11-11 TE - transmitter enable 11-11 TIE - transmit interrupt enable 11-11 SCDR -- serial communications data register 11-9 SCI baud rate selection 11-16 block diagram 11-2 data format 11-5 receiver wake-up 11-5 start bit detection 11-7 SCK 2-6 SCP1, SCP0 bits in BAUD 11-15 SCSR -- serial communications status register 11-12 FE - framing error flag 11-14 IDLE - idle line detected flag 11-13 NF - noise error flag 11-14 OR - overrun error flag 11-13 RDRF - receive data register full flag 11-13 TC - transmit complete flag 11-13 TDRE - transmit data register empty flag 11-13 SCT2, SCT1, SCT0 bits in BAUD 11-15 SOR 2-4 IRQ -- interrupt sensitivity 2-4 KEYCLR -- keyboard interrupt clear 2-4 KEYMUX -- multiplex bit for access of interrupt flag 2-4 LVIF, LVIE, LVION -- low voltage interrupt bits 2-4 PUEN -- PORTC pull-up enable 2-4 SC -- system clock option 2-4 SP - stack pointer 15-2 T T8 bit in SCCR1 11-10 TC bit in SCSR 11-13 TCAP1 2-6 TCAP1, TCAP2 bits in TSR 6-8 TCAP2 2-6 TCAP3 2-6 TCAP4 2-6 TCIE bit in SCCR2 11-11 TCMP1 2-6 TCMP2 2-6 TCR1 -- timer control register 1 6-4 CO1E - compare output enable bit 1 6-5 IC1IE - input capture interrupt enable 1 6-5 IC2IE - input capture interrupt enable 2 6-5 IEDG1 - input edge bit 1 6-5 IEDG2 - input edge bit 2 6-6 OC1IE - output compare interrupt enable 1 6-5 OLVL1 - output level bit 1 6-6 TOIE - timer overflow interrupt enable 6-5 TCR2 -- timer control register 2 6-4 CO2E - compare output enable bit 2 6-6 OC2IE - output compare interrupt enable 2 6-6 MC68HC05F32 For More Information On This Product, Go to: www.freescale.com INDEX MOTOROLA xxi Freescale Semiconductor, Inc. OLVL2 - output level bit 2 6-6 TDO 2-6 SCI transmit data out 11-8 TDRE bit in SCSR 11-13 TE bit in SCCR2 11-11 thermal characteristics 16-2 TIE bit in SCCR2 11-11 timing diagrams programmable timer 6-13 TNCR -- tone control register MS1, MS0 - melody select for operation 7-4 TGEC - tone generator enable column path 7-5 TGER - tone generator enable row path 7-5 TNOE - tone output enable 7-5 TNO, TNX pins 2-7 TNOE bit in TNCR 7-5 TOF bit in TSR 6-7 TOIE bit in TCR1 6-5 TSR -- timer status register 6-7 IC1F, IC2F - input capture flags 6-7 OC1F, OC2F - output compare flags 6-7 TACP1, TCAP2 - input capture status flags 6-8 TOF - timer overflow status flag 6-7 Freescale Semiconductor, Inc... V VDD 2-5 VLCD 2-7 VRH 2-6 VSS 2-5 W WAIT mode 2-2 WAKE bit in SCCR1 11-10 watchdog timer 14-2 WCOL 10-8 WCOL bit in SPSR 10-8 WTLCDO bit in LCD 8-9 X X - index register 15-2 Z Z-bit in CCR 15-3 MOTOROLA xxii For More Information On This Product, Go to: www.freescale.com INDEX MC68HC05F32 Freescale Semiconductor, Inc. CUSTOMER FEEDBACK QUESTIONNAIRE (MC68HC05F32/D) Motorola wishes to continue to improve the quality of its documentation. We would welcome your feedback on the publication you have just received. Having used the document, please complete this card (or a photocopy of it, if you prefer). 1. How would you rate the quality of the document? Check one box in each category. Excellent Organization Readability Understandability Accuracy Illustrations Comments: Poor Excellent Tables Table of contents Index Page size/binding Overall impression Poor Freescale Semiconductor, Inc... t t t t t t t t t t t t t t t t t t t t t t t Not at all t t t t t t t t t t t t t t t t t t t t 2. What is your intended use for this document? If more than one option applies, please rank them (1, 2, 3). Selection of device for new application System design Training purposes Other t Please specify: 3. How well does this manual enable you to perform the task(s) outlined in question 2? Completely Comments: - Cut along this line to remove - tttt 4. How easy is it to find the information you are looking for? Easy Difficult Comments: tttt 5. Is the level of technical detail in the following sections sufficient to allow you to understand how the device functions? Too little detail SECTION 1 INTRODUCTION SECTION 2 MODES OF OPERATION AND PIN DESCRIPTIONS SECTION 3 MEMORY AND REGISTERS SECTION 4 PARALLEL INPUT/OUTPUT PORTS SECTION 5 CORE TIMER SECTION 6 16-BIT PROGRAMMABLE TIMER SECTION 7 DTMF/MELODY GENERATOR SECTION 8 LIQUID CRYSTAL DISPLAY DRIVER MODULE SECTION 9 A/D CONVERTER SECTION 10 SERIAL PERIPHERAL INTERFACE SECTION 11 SERIAL COMMUNICATIONS INTERFACE SECTION 12 PULSE WIDTH MODULATOR SECTION 13 32 KHZ CLOCK SYSTEM SECTION 14 RESETS AND INTERRUPTS SECTION 15 CPU CORE AND INSTRUCTION SET SECTION 16 ELECTRICAL SPECIFICATIONS SECTION 17 MECHANICAL DATA SECTION 18 ORDERING INFORMATION SECTION 19 APPENDICES Have you found any errors? If so, please comment: Too much detail 6. t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t 7. From your point of view, is anything missing from the document? If so, please say what: For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 8. How could we improve this document? 9. How would you rate Motorola's documentation? Excellent - In general - Against other semiconductor suppliers Poor tttt tttt t t 10. Which semiconductor manufacturer provides the best technical documentation? 11. Which company (in any field) provides the best technical documentation? 12. How many years have you worked with microprocessors? Less than 1 year Freescale Semiconductor, Inc... t 1-3 years t 3-5 years More than 5 years - Second fold back along this line - By air mail Par avion IBRS NUMBER PHQ-B/207/G CCRI NUMERO PHQ-B/207/G NE PAS AFFRANCHIR - Cut along this line to remove - - First fold back along this line - NO STAMP REQUIRED REPONSE PAYEE GRANDE-BRETAGNE Motorola Ltd., Colvilles Road, Kelvin Industrial Estate, EAST KILBRIDE, G75 8BR. GREAT BRITAIN. Semiconductor Products Sector F.A.O. Technical Publications Manager (re: MC68HC05F32/D) - Third fold back along this line - 13. Currently there is some discussion in the semiconductor industry regarding a move towards providing data sheets in electronic form. If you have any opinion on this subject, please comment. 14. We would be grateful if you would supply the following information (at your discretion), or attach your card. Name: Position: Department: Company: Address: Phone No: FAX No: Thank you for helping us improve our documentation, Graham Forbes, Technical Publications Manager, Motorola Ltd., Scotland. For More Information On This Product, Go to: tuck this edge into opposite flap - - Finally, www.freescale.com Freescale Semiconductor, Inc. INTRODUCTION MODES OF OPERATION AND PIN DESCRIPTIONS MEMORY AND REGISTERS PARALLEL INPUT/OUTPUT PORTS CORE TIMER 16-BIT PROGRAMMABLE TIMER DTMF/MELODY GENERATOR LIQUID CRYSTAL DISPLAY DRIVER MODULE A/D CONVERTER SERIAL PERIPHERAL INTERFACE SERIAL COMMUNICATIONS INTERFACE PULSE WIDTH MODULATOR 32 KHZ CLOCK SYSTEM RESETS AND INTERRUPTS CPU CORE AND INSTRUCTION SET ELECTRICAL SPECIFICATIONS MECHANICAL DATA ORDERING INFORMATION MC68HC705F32 For More Information On This Product, Go to: www.freescale.com 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 A Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 A INTRODUCTION MODES OF OPERATION AND PIN DESCRIPTIONS MEMORY AND REGISTERS PARALLEL INPUT/OUTPUT PORTS CORE TIMER 16-BIT PROGRAMMABLE TIMER DTMF/MELODY GENERATOR LIQUID CRYSTAL DISPLAY DRIVER MODULE A/D CONVERTER SERIAL PERIPHERAL INTERFACE SERIAL COMMUNICATIONS INTERFACE PULSE WIDTH MODULATOR 32 KHZ CLOCK SYSTEM RESETS AND INTERRUPTS CPU CORE AND INSTRUCTION SET ELECTRICAL SPECIFICATIONS MECHANICAL DATA ORDERING INFORMATION MC68HC705F32 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Freescale Semiconductor, Inc... For More Information On This Product, Go to: www.freescale.com 15 1 2 3 4 5 6 7 8 9 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... 10 11 12 13 14 15 For More Information On This Product, Go to: www.freescale.com How to reach us: MfaxTM: RMFAX0@email.sps.mot.com - TOUCHTONE (602) 244-6609 INTERNET: http://www.mot.com/SPS/ USA/EUROPE: Motorola Literature Distribution; P.O. Box 5405; Denver, Colorado 80217. 303-675-2140 JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, Toshikatsu Otsuki, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 81-3-3521-8315 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 |
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